is42s16800a1 Integrated Silicon Solution, Inc., is42s16800a1 Datasheet - Page 11

• Manufacturer Part Number: is42s16800a1
• Description: 8meg 128-mbit Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ
bus.
Minimum Read to Write Interval
IS42S16800A1
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00B
05/01/06
CK
DQM
COMMAND
CAS latency = 2
t
CAS latency = 3
t
CK2
CK3
: “H” or “L”
,
,
DQs
DQs
T0
NOP
T1
READ A
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
WRITE A
T2
DIN A
DIN A
0
0
T3
DIN A
DIN A
NOP
1
1
1-800-379-4774
T4
DIN A
DIN A
NOP
2
2
T5
DIN A
DIN A
NOP
(Burst Length = 4, CAS latency = 2, 3)
N
3
3
T6
NOP
©
T7
NOP
T8
NOP
ISSI
11
®