is42s32800g-7bli Integrated Silicon Solution, Inc., is42s32800g-7bli Datasheet

Page 1

... IS42S32800G IS45S32800G 256Mb SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – ...

Page 2

... IS42S32800G, IS45S32800G DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 268,435,456 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is orga- nized as 4,096 rows by 512 columns by 32 bits. ...

Page 3

... IS42S32800G, IS45S32800G PIN CONFIGURATION PACKAGE CODE BALL TF-BGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input ...

Page 4

... IS42S32800G, IS45S32800G PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin Input Pin CS DQM0-DQM3 Input Pin DQ0-DQ31 Input/Output Pin Input Pin RAS Input Pin WE V Power Supply Pin ddq V Power Supply Pin ...

Page 5

... IS42S32800G, IS45S32800G GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A8 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...

Page 6

... IS42S32800G, IS45S32800G COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) ...

Page 7

... IS42S32800G, IS45S32800G CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit ...

Page 8

... IS42S32800G, IS45S32800G FUNCTIONAL TRUTH TABLE Current State CS RAS CAS Idle Row Active Read ...

Page 9

... IS42S32800G, IS45S32800G FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS Read with auto H × × Precharging Write with Auto H × × Precharge ...

Page 10

... IS42S32800G, IS45S32800G FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS Write Recovering H × × Write Recovering H × × with Auto Precharge ...

Page 11

... IS42S32800G, IS45S32800G CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

Page 12

... IS42S32800G, IS45S32800G STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 12 SELF SELF exit MRS IDLE CKE CKE ACT CKE Row Active CKE BST BST Read Write Read Write Precharge Self ...

Page 13

... IS42S32800G, IS45S32800G ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 14

... IS42S32800G, IS45S32800G DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps (In Power-Down Mode) i Precharge Standby Current (2) dd2n (In Non Power-Down Mode) I Precharge Standby Current dd2ns (In Non Power-Down Mode) I Active Standby Current dd3p (Power-Down Mode) ...

Page 15

... IS42S32800G, IS45S32800G AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width ch t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time ...

Page 16

... IS42S32800G, IS45S32800G OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...

Page 17

... IS42S32800G, IS45S32800G AC TEST CONDITIONS Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A ...

Page 18

... IS42S32800G, IS45S32800G FUNCTIONAL DESCRIPTION Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command which is then followed by a READ orWRITE command ...

Page 19

... IS42S32800G, IS45S32800G INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM0-DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µ ...

Page 20

... IS42S32800G, IS45S32800G AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = Auto NOP Refresh ...

Page 21

... IS42S32800G, IS45S32800G SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode Note: 1. Self-Refresh Mode is not supported for A2 grade with T Integrated Silicon Solution, Inc ...

Page 22

... IS42S32800G, IS45S32800G REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...

Page 23

... IS42S32800G, IS45S32800G BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...

Page 24

... IS42S32800G, IS45S32800G CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

Page 25

... IS42S32800G, IS45S32800G CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...

Page 26

... IS42S32800G, IS45S32800G READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

Page 27

... IS42S32800G, IS45S32800G diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s) ...

Page 28

... IS42S32800G, IS45S32800G RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL NOP NOP NOP NOP n+1 D n+2 OUT OUT OUT NOP NOP ...

Page 29

... IS42S32800G, IS45S32800G CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 NOP NOP NOP READ BANK, COL b ...

Page 30

... IS42S32800G, IS45S32800G RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - READ ...

Page 31

... IS42S32800G, IS45S32800G READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 BURST NOP NOP NOP TERMINATE ...

Page 32

... IS42S32800G, IS45S32800G ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 ...

Page 33

... IS42S32800G, IS45S32800G READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x32: A9, A11 = " ...

Page 34

... IS42S32800G, IS45S32800G READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A9, A11 = " ...

Page 35

... IS42S32800G, IS45S32800G READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 NOP NOP NOP PRECHARGE BANK ...

Page 36

... IS42S32800G, IS45S32800G WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A8 COLUMN ADDRESS A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

Page 37

... IS42S32800G, IS45S32800G WRITE BURST CLK COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL ...

Page 38

... IS42S32800G, IS45S32800G WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP PRECHARGE BANK (a or all) ...

Page 39

... IS42S32800G, IS45S32800G WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 NOP NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST ...

Page 40

... IS42S32800G, IS45S32800G WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) x32: A9, A11 = "Don't Care" ...

Page 41

... IS42S32800G, IS45S32800G WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = 4 2) x32: A9, A11 = "Don't Care" ...

Page 42

... IS42S32800G, IS45S32800G ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BANK 0 BA0, BA1 BANK 0 ...

Page 43

... IS42S32800G, IS45S32800G CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

Page 44

... IS42S32800G, IS45S32800G CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM0 - DQM3 A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. ...

Page 45

... IS42S32800G, IS45S32800G PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks.The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or ...

Page 46

... IS42S32800G, IS45S32800G POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles All banks idle, enter Precharge all active banks power-down mode Note: x32: A9, A11 = " ...

Page 47

... IS42S32800G, IS45S32800G BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access ...

Page 48

... IS42S32800G, IS45S32800G WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered ...

Page 49

... IS42S32800G, IS45S32800G SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC ...

Page 50

... IS42S32800G, IS45S32800G SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x32: A9, A11 = " ...

Page 51

... IS42S32800G, IS45S32800G READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD ...

Page 52

... IS42S32800G, IS45S32800G READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A9, A11 = " ...

Page 53

... IS42S32800G, IS45S32800G SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC ...

Page 54

... IS42S32800G, IS45S32800G SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x32: A9, A11 = " ...

Page 55

... IS42S32800G, IS45S32800G WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) x32: A9, A11 = " ...

Page 56

... IS42S32800G, IS45S32800G WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD ...

Page 57

... IS42S32800G-75EBL 90-Ball TF-BGA, Lead-free IS42S32800G-75EB 90-Ball TF-BGA Order Part No. Package IS42S32800G-6BI 90-Ball TF-BGA IS42S32800G-6BLI 90-Ball TF-BGA, Lead-free IS42S32800G-7BI 90-Ball TF-BGA IS42S32800G-7BLI 90-Ball TF-BGA, Lead-free IS42S32800G-75EBLI 90-Ball TF-BGA, Lead-free IS42S32800G-75EBI 90-Ball TF-BGA Order Part No. Package IS45S32800G-6BLA1 90-Ball TF-BGA, Lead-free IS45S32800G-7BA1 90-Ball TF-BGA ...

Page 58

... IS42S32800G, IS45S32800G 58 D1 Integrated Silicon Solution, Inc. - www.issi.com Rev. 00A 07/12/2010 ...