is42sm16800g-6bli Integrated Silicon Solution, Inc., is42sm16800g-6bli Datasheet - Page 29

• Manufacturer Part Number: is42sm16800g-6bli
• Description: 2m X 16bits X 4banks Mobile Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

Rev. 00A | Dec. 2010
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
5. Parameter guaranteed by design.
reduce the data rate.
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
data element will meet tOH before going High-Z.
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
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