is43lr32200b-6bl Integrated Silicon Solution, Inc., is43lr32200b-6bl Datasheet - Page 40

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is43lr32200b-6bl

Manufacturer Part Number
is43lr32200b-6bl
Description
512k X 32bits X 4banks Mobile Ddr Sdram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
Rev. 00A | Feb. 2011
Clock Stop Mode
Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption during idle periods of
the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
• The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion,
• The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;
• CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with CK held
LOW and /CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command have to be issued for at least one clock
cycle before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics.
Figure37 illustrates the clock stop mode:
• Initially the device is in clock stop mode;
• The clock is restarted with the rising edge of T0 and a NOP on the command inputs;
• With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this
• T
• The timing condition of this access command is met with the completion of T
Figure 37 : Clock Stop Mode
including any data-out during read bursts; the number of required clock pulses per access command depends on the device's AC timing
parameters and the clock frequency;
access command has completed;
command and the clock is then stopped.
n
is the last clock pulse required by the access command latched with T1.
DQ,DQS
/CLK
CMD
ADD
CKE
CLK
stopped
High
Clock
Stop Mode
Exit Clock
NOP
T0
Command
Valide
CMD
Vail
T1
(High – Z)
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Timing Condition
NOP
T2
- dram@issi.com
Enter Clock
Stop Mode
NOP
n
T
; therefore Tn is the last clock pulse required by this
n
NOP
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IS43/46LR32200B
Advanced Information
40

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