m24128-wmw6t STMicroelectronics, m24128-wmw6t Datasheet - Page 5

• Manufacturer Part Number: m24128-wmw6t
• Description: 256/128 Kbit Serial Eeprom Without Chip Enable Lines
• Manufacturer: STMicroelectronics

Table 4. Operating Modes
Note: 1. X =
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
V
Mode
IH
or V
IL
.
NO ACK
DEV SEL
DEV SEL
RW bit
1
0
1
1
0
0
DATA IN N
R/W
R/W
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
WC
V
V
X
X
X
X
IL
IL
1
ACK
ACK
Data Bytes
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
BYTE ADDR
BYTE ADDR
1
1
1
64
1
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
Initial Sequence
DATA IN 2
M24256, M24128
AI01120C
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