m95512-dr STMicroelectronics, m95512-dr Datasheet - Page 23

• Manufacturer Part Number: m95512-dr
• Description: 512kbit Serial Spi Bus Eeprom With High Speed Clock
• Manufacturer: STMicroelectronics

M95512-W, M95512-R, M95512-DR
6.6
Note:
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for
a period t
(WIP) bit is reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 128 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
W
(as specified in
Figure
Figure
0
1
High Impedance
12, to send this instruction to the device, Chip Select (S) is first driven
2
12, Chip Select (S) is driven high after the eighth bit of the data byte
Instruction
3
W
4
Table 16
is internally executed as a sequence of two consecutive
5
Doc ID 11124 Rev 12
6
7
and
15
8
14 13
Table
9 10
16-Bit Address
18), at the end of which the Write in Progress
3
20 21 22 23 24 25 26 27
2
1
0
7
6
Figure
5
Data Byte
4
13., the next byte of
3
28 29 30
2
1
Instructions
0
31
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