M95512-DRMN6TP STMicroelectronics, M95512-DRMN6TP Datasheet
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M95512-DRMN6TP
Specifications of M95512-DRMN6TP
Related parts for M95512-DRMN6TP
M95512-DRMN6TP Summary of contents
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... Write Protect: quarter, half or whole memory array ■ High-speed clock: 10 MHz ■ Single supply voltage: – 2 5.5 V for M95512-W – 1 5.5 V for M95512-R and M95512- DR – 1 5.5 V for M95512-DF ■ Operating temperature range: from -40° +85°C ■ Enhanced ESD protection ■ ...
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... Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/51 M95512-W M95512-R M95512-DR M95512- Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 11124 Rev 20 ...
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... Write to Memory Array (WRITE 6.6.1 6.7 Read Identification Page (available only in M95512-D devices 6.8 Write Identification Page (available only in M95512-D devices 6.9 Read Lock Status (available only in M95512-D devices 6.10 Lock ID (available only in M95512-D devices Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... M95512-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Operating conditions (M95512-W, device grade Table 9. Operating conditions (M95512-R and M95512-DR, device grade Table 10. Operating conditions (M95512-DF, device grade Table 11. AC measurement conditions Table 12. ...
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... SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 43 Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline Figure 26. M95512-DFCS6TP/K – WLCSP 8-bump wafer-level chip scale package outline . . . . . . . 46 Doc ID 11124 Rev 20 List of figures 5/51 ...
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... The M95512 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 65536 x 8 bits, accessed through the SPI bus. The M95512-W can operate with a supply voltage from 2 5.5 V, the M95512-R and M95512-DR can operate with a supply voltage from 1 5.5 V, and the M95512-DF can operate with a supply voltage from 1 5.5 V, over an ambient temperature range of -40 ° ...
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... See Section 10: Package mechanical data Figure 3. WLCSP connections for M95512-DFCS6TP/K (top view, marking side, with balls on the underside) Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light ...
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... Memory organization 2 Memory organization The memory is organized as shown in the following figure. Figure 4. Block diagram HOLD 8/51 M95512-W M95512-R M95512-DR M95512-DF High voltage Control logic generator I/O shift register Data Address register register and counter Identification page X decoder Doc ID 11124 Rev 20 Status ...
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... M95512-W M95512-R M95512-DR M95512-DF 3 Signal description During all operations (min (max All of the input and output signals must be held high or low (according to voltages specified described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C) ...
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... Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 V supply voltage the supply voltage. CC 3.8 V ground the reference for all signals, including the V SS 10/51 M95512-W M95512-R M95512-DR M95512-DF supply voltage. CC Doc ID 11124 Rev 20 ...
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... M95512-W M95512-R M95512-DR M95512-DF 4 Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. ...
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... Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 6. SPI modes supported CPOL CPHA 12/51 M95512-W M95512-R M95512-DR M95512-DF MSB Doc ID 11124 Rev 20 Figure 6, is the clock polarity when the MSB AI01438B ...
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... M95512-W M95512-R M95512-DR M95512-DF 5 Operating features 5.1 Supply voltage (V 5.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V in Section 9: DC and AC end of the transmission of the instruction and, for a Write instruction, until the completion of ...
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... This resets the internal logic, except the WEL and WIP bits of the Status Register the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. 14/51 M95512-W M95512-R M95512-DR M95512- (a)(b) ...
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... M95512-W M95512-R M95512-DR M95512-DF The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions ...
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... Read Lock Status Lock ID 1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care. 16/51 M95512-W M95512-R M95512-DR M95512-DF Description Write Enable Write Disable Read Status Register ...
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... M95512-W M95512-R M95512-DR M95512-DF 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: ● Power-up ● WRDI instruction execution ● WRSR instruction completion ● WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence 18/51 M95512-W M95512-R M95512-DR M95512- send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance ...
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... M95512-W M95512-R M95512-DR M95512-DF 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. The instruction sequence is shown in Figure 11. Write Status Register (WRSR) sequence 20/51 M95512-W M95512-R M95512-DR M95512- Figure 11 ...
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... M95512-W M95512-R M95512-DR M95512-DF Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self- timed Write cycle that takes t and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle t , and 0 when the Write cycle is complete ...
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... D High Impedance Q If Chip Select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. 22/51 M95512-W M95512-R M95512-DR M95512-DF 12, to send this instruction to the device, Chip Select (S) is first driven ...
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... M95512-W M95512-R M95512-DR M95512-DF When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle ...
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... C Instruction Data Byte 24/51 M95512-W M95512-R M95512-DR M95512-DF is internally executed as a sequence of two consecutive 16-Bit Address Data Byte 3 ...
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... M95512-W M95512-R M95512-DR M95512-DF 6.6.1 Cycling with Error Correction Code (ECC) M95512 and M95512-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value ...
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... Instructions 6.7 Read Identification Page (available only in M95512-D devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D) ...
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... M95512-W M95512-R M95512-DR M95512-DF 6.8 Write Identification Page (available only in M95512-D devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D) ...
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... Instructions 6.9 Read Lock Status (available only in M95512-D devices) The Read Lock Status instruction (see Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D) ...
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... M95512-W M95512-R M95512-DR M95512-DF 6.10 Lock ID (available only in M95512-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high ...
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... Initial delivery state The device is delivered with the memory array bits and identification page bits set to all 1s (each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 30/51 M95512-W M95512-R M95512-DR M95512-DF Doc ID 11124 Rev 20 ...
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... M95512-W M95512-R M95512-DR M95512-DF 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 8. Operating conditions (M95512-W, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 9. Operating conditions (M95512-R and M95512-DR, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 10. Operating conditions (M95512-DF, device grade 6) Symbol V ...
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... M95512-W M95512-R M95512-DR M95512-DF Table 12. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested Table 13. Cycling performance by groups of four bytes Symbol Parameter Ncycle Write cycle endurance 1. Cycling performance for products identified by process letters KB. ...
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... DC and AC parameters Table 15. DC characteristics (previous M95512-W products, device grade 6) Symbol Parameter Input leakage I LI current Output leakage I LO current Supply current I CC (Read) Supply current (2) I CC0 (Write) Supply current I (Standby Power CC1 mode) V Input low voltage IL V Input high voltage ...
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... M95512-W M95512-R M95512-DR M95512-DF Table 16. DC characteristics (M95512-W products, device grade 6) Symbol Parameter Input leakage current Output leakage current C = 0.1 V Supply current Q = open I CC (Read 0.1 V Supply current (2) I During t CC0 (Write) Supply current (Standby Power CC1 ...
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... V Output low voltage OL V Output high voltage the application uses the M95512-R or M95512-DR with 2.5 V V Table 16 and Table 15 instead of the above table. 2. Max clock frequency is 5 MHz (was 2 MHz for previous products identified with process letters AB). 3. Characterized only, not tested in production. ...
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... OL V Output high voltage the application uses the M95512-DF device with 2.5 V V instead of the above table. 2. Characterized only, not tested in production µA for devices identified from date code 301 (year 2013, W01), 3 µA for previous devices Test conditions in addition to those ...
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... DC and AC parameters Table 19. AC characteristics (previous M95512-W products, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... M95512-W M95512-R M95512-DR M95512-DF Table 20. AC characteristics (M95512-W products, device grade 6) Test conditions: refer to Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time ...
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... The test flow guarantees the AC parameter values defined in this table (when V parameter values defined in AC characteristics tables for M95512-W (when the application uses the device at 2.5 V V above table. 3. Not for new designs (previous products are identified by process letters AB) 4 ...
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... M95512-W M95512-R M95512-DR M95512-DF Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 11124 Rev 20 DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV ...
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... DC and AC parameters Figure 22. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN 42/51 M95512-W M95512-R M95512-DR M95512-DF tCH tCHCL tCL tQLQH tQHQL Doc ID 11124 Rev 20 tSHSL tSHQZ AI01449f ...
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... M95512-W M95512-R M95512-DR M95512-DF 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline A2 1 ...
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... TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to four decimal digits. 44/51 M95512-W M95512-R M95512-DR M95512- millimeters Typ Min Max 1.200 0.050 0.150 1 ...
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... M95512-W M95512-R M95512-DR M95512-DF Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline Drawing is not to scale. 2. The central pad (area the above illustration) is internally pulled to V connected to any other voltage or signal line on the PCB, for example during the soldering process. ...
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... Package mechanical data Figure 26. M95512-DFCS6TP/K – WLCSP 8-bump wafer-level chip scale package outline Reference Wafer back side 1. Drawing is not to scale. 46/51 M95512-W M95512-R M95512-DR M95512- aaa (4X) Side view Bump eee Z ccc Ø ddd M Z Ø Rotated 90 ° Doc ID 11124 Rev 20 ...
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... M95512-W M95512-R M95512-DR M95512-DF Table 25. M95512-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data Symbol A 0.540 A1 0.190 A2 0.350 b 0.270 D 1.271 E 1.937 e 1.000 e1 0.866 e2 0.500 e3 0.433 F 0.202 G 0.469 N aaa 0.110 bbb 0.110 ccc 0.110 ddd 0.060 eee 0.060 1. Values in inches are converted from mm and rounded to four decimal digits. ...
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... Manufacturing technology code 1. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. 48/51 M95512-W M95512-R M95512-DR M95512-DF M95512 Doc ID 11124 Rev ...
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... Section 4.5: Data protection and protocol control Section 4.4: Status register: – Table 2: Write-protected block size Deleted: – Table 25: Available M95512 products (package, voltage range, temperature grade) – Table 26: Available M95512-DR products (package, voltage range, temperature grade) Renamed Figure 2. 15 Added UFDFPN8 MC package. ...
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... Table 20: AC characteristics (M95512-W products, device grade 6). Updated: – Section 7.2: Initial delivery state 20 – I values in Table 16, CC1 – Note 1 in Table 15: DC characteristics (previous M95512-W products, device grade 6) Doc ID 11124 Rev 20 Changes underside). Table 17, Table 18, Table 19, Table Table 17. Table 17 and Table 18 ...
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... M95512-W M95512-R M95512-DR M95512-DF Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...