w25q16cl Winbond Electronics Corp America, w25q16cl Datasheet
w25q16cl
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w25q16cl Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: July 08, 2010 - 1 - Preliminary - Revision A W25Q16CL ...
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... Block Protect Bits (BP2, BP1, BP0)....................................................................................13 11.1.4 Top/Bottom Block Protect (TB)...........................................................................................13 11.1.5 Sector/Block Protect (SEC) ................................................................................................13 11.1.6 Complement Protect (CMP) ...............................................................................................14 11.1.7 Status Register Protect (SRP1, SRP0)...............................................................................14 11.1.8 Erase/Program Suspend Status (SUS) ..............................................................................14 11.1.9 Security Register Lock Bits (LB3, LB2, LB1) ......................................................................14 11.1.10 Quad Enable (QE) ............................................................................................................15 11.1.11 Status Register Memory Protection (CMP = 0).................................................................16 Table of Contents - 2 - W25Q16CL ...
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... Read Manufacturer / Device ID Dual I/O (92h) .................................................................52 11.2.33 Read Manufacturer / Device ID Quad I/O (94h)................................................................53 11.2.34 Read Unique ID Number (4Bh).........................................................................................54 11.2.35 Read JEDEC ID (9Fh) ......................................................................................................55 11.2.36 Read SFDP Register (5Ah) ..............................................................................................56 11.2.37 Erase Security Registers (44h).........................................................................................59 11.2.38 Program Security Registers (42h) ....................................................................................60 11.2.39 Read Security Registers (48h)..........................................................................................61 Publication Release Date: July 08, 2010 - 3 - Preliminary - Revision A W25Q16CL ...
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... SOIC 150-mil (Package Code SN) ........................................................................... 69 13.2 8-Pin SOIC 208-mil (Package Code SS) ........................................................................... 70 13.3 8-Pin PDIP 300-mil (Package Code DA)............................................................................ 71 13.4 8-Pad WSON 6x5mm (Package Code ZP) ........................................................................ 72 13.5 16-Pin SOIC 300-mil (Package Code SF).......................................................................... 74 14. ORDERING INFORMATION .......................................................................................................... 75 14.1 Valid Part Numbers and Top Side Marking........................................................................ 76 15. REVISION HISTORY...................................................................................................................... W25Q16CL ...
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... Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16CL has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... DO ( /WP (IO /WP ( GND GND Figure 1a. W25Q16CL Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM DO (IO DO (IO /WP (IO /WP (IO GND GND Figure 1b. W25Q16CL Pad Assignments, 8-pad WSON 6x5-mm (Package Code ZP ...
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... PIN CONFIGURATION PDIP 300-MIL /CS /CS DO ( /WP (IO /WP ( GND GND Figure 1c. W25Q16CL Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 150/208-MIL, PDIP 300-MIL AND WSON 6X5-MM PIN NO. PIN NAME 1 / (IO1) 3 /WP (IO2) 4 GND 5 DI (IO0) ...
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... PIN CONFIGURATION SOIC 300-MIL /HOLD (IO /HOLD ( VCC VCC N/C N/C N/C N/C N/C N/C N/C N/C /CS / Figure 1d. W25Q16CL Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PIN NO. PIN NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N (IO1) 9 /WP (IO2) 10 GND ...
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... Package Types W25Q16CL is offered in an 8-pin plastic 150-mil or 208-mil width SOIC (package code SN & SS) and 6x5-mm WSON (package code ZP) as shown in figure 1a and 1b respectively. The 300-mil 8-pin PDIP (package code DA) is another option of package selections as shown in figure 1c. The W25Q16CL is also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1d. Package diagrams and dimensions are illustrated at the end of this datasheet ...
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... SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q16CL Serial Flash Memory Block Diagram 0000FFh 0000FFh xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • ...
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... For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 10.1.2 Dual SPI Instructions The W25Q16CL supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices ...
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... One Time Program (OTP) write protection * Note: This feature is available upon special order. Please contact Winbond for details. Upon power- power-down, the W25Q16CL will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 38). While reset, all WI operations are disabled and no instructions are recognized ...
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... The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. Publication Release Date: July 08, 2010 - 13 - W25Q16CL , and ...
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... When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again until the next power-down, power-up cycle. Status Register is permanently protected and can not be (2) written to W25Q16CL (1) ...
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... TB TB BP2 BP2 Figure 3a. Status Register-1 S15 S15 S14 S14 S13 S13 SUS SUS CMP CMP LB3 LB3 RESERVED RESERVED Figure 3b. Status Register W25Q16CL BP1 BP1 BP0 BP0 WEL BUSY WEL BUSY S12 S12 S11 S11 ...
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... X Notes don’t care Lower Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. W25Q16CL (16M-BIT) MEMORY PROTECTION PROTECTED PROTECTED BLOCK(S) ADDRESSES NONE NONE 31 1F0000h – 1FFFFFh 30 and 31 1E0000h – ...
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... X Notes don’t care Lower Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. W25Q16CL (16M-BIT) MEMORY PROTECTION PROTECTED PROTECTED BLOCK(S) ADDRESSES 0 thru 31 000000h – 1FFFFFh 0 thru 30 000000h – 1EFFFFh 0 thru 29 000000h – ...
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... INSTRUCTIONS The instruction set of the W25Q16CL consists of thirty five basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 FFh - 19 - W25Q16CL (1) BYTE 5 BYTE 6 A7–A0 (D7–D0) (3) A7–A0 (D7–D0, …) A7–A0 A7–A0 A7–A0 Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... A23-A0, M7-M0 (x,x, D7-D0, …) (4) (3) A23-A0, M7-M0 (D7-D0, …) (4) xxxxxx, W6-W4 Set Burst with Wrap Input IO0 = W4, x IO1 = W5, x IO2 = IO3 = W25Q16CL BYTE 4 BYTE 5 BYTE 6 A7-A0 (D7-D0) A7-A0 dummy (D7-D0) A7-A0 dummy (D7-D0, …) A7-A0 dummy (D7-D0, …) (1) (D7-D0, … ...
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... A23-A8 A7-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy 00h 00h A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15– W25Q16CL BYTE 4 BYTE 5 BYTE 6 (1) dummy (ID7-ID0) 00h (MF7-MF0) (ID7-ID0) (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) (ID7-ID0) Capacity dummy dummy (ID63-ID0) A7–A0 dummy A7– ...
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... Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit only valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram Figure 4. Write Enable Instruction Sequence Diagram Instruction (50h W25Q16CL ...
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... DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Instruction Sequence Diagram - 23 - W25Q16CL Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... However, SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for these bits. Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored when power on again W25Q16CL ...
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... Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. Please refer to 11.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. Figure 8. Write Status Register Instruction Sequence Diagram (See AC Characteristics). W Publication Release Date: July 08, 2010 - 25 - W25Q16CL (See AC SHSL2 Preliminary - Revision A ...
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... The Read Data instruction sequence is shown in figure Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 9. Read Data Instruction Sequence Diagram - 26 - W25Q16CL R ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 10. Fast Read Instruction Sequence Diagram - 27 - W25Q16CL Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 11. Fast Read Dual Output Instruction Sequence Diagram and IO . This allows data to be transferred from the W25Q16CL pin should be high-impedance prior to the falling edge of the first data 0 ...
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... IO executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q16CL at four times the rate of standard SPI devices. ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 11.2.20 for detail descriptions). Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 ≠ 10 W25Q16CL ...
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... Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: July 08, 2010 - 31 - W25Q16CL Preliminary - Revision A ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 11.2.20 for detail descriptions). Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5 The Quad I/O dramatically reduces instruction overhead . - 32 - W25Q16CL and IO and four Dummy 2 3 Byte 1 Byte 1 Byte 2 Byte 2 ≠ ...
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... The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 11.2.18 for detail descriptions. Publication Release Date: July 08, 2010 - 33 - W25Q16CL Preliminary - Revision A ...
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... Byte 2 Byte 2 Byte 1 Byte 1 ≠ W25Q16CL Byte 3 ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Publication Release Date: July 08, 2010 - 35 - W25Q16CL Preliminary - Revision A ...
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... Byte 2 Byte 2 Byte 3 Byte 3 Byte 1 Byte W25Q16CL ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Publication Release Date: July 08, 2010 - 37 - W25Q16CL Preliminary - Revision A ...
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... Wrap instruction should be issued to set The default value of W4 upon power the case of a system Reset while recommended that the controller issues a Set Burst with Wrap instruction to reset prior to any normal Read instructions since W25Q16CL does not have a hardware Reset Pin. ...
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... Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O Since W25Q16CL does not have a hardware Reset pin the controller resets while W25Q16CL is set to Continuous Mode Read, the W25Q16CL will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. Figure 19. Page Program Instruction Sequence Diagram - 40 - W25Q16CL ...
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... Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 20. Figure 20. Quad Input Page Program Instruction Sequence Diagram , and IO . The Quad Page Program can Publication Release Date: July 08, 2010 - 41 - W25Q16CL Preliminary - Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Sector Erase SE Figure 21. Sector Erase Instruction Sequence Diagram - 42 - W25Q16CL ...
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... Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 22. 32KB Block Erase Instruction Sequence Diagram 1 (See AC Characteristics). While the Block Erase BE Publication Release Date: July 08, 2010 - 43 - W25Q16CL Preliminary - Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 23. 64KB Block Erase Instruction Sequence Diagram (See AC Characteristics). While the Block Erase cycle W25Q16CL ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 24. Chip Erase Instruction Sequence Diagram - 45 - W25Q16CL Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. Figure 25. Erase/Program Suspend Instruction Sequence ” (See AC Characteristics) is required SUS ” following the preceding SUS - 46 - W25Q16CL ...
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... Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “t Figure 26. Erase/Program Resume Instruction Sequence ” following a previous Resume instruction. SUS - 47 - W25Q16CL Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 27. Deep Power-down Instruction Sequence Diagram - 48 - W25Q16CL ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. The Device ID values for the W25Q16CL is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
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... Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram - 50 - W25Q16CL ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 29. The Device ID values for the W25Q16CL is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... CLK with most significant bits (MSB) first as shown in figure 30. The Device ID values for the W25Q16CL is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 31. The Device ID values for the W25Q16CL is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q16CL device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the W25Q16CL provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Read SFDP Register (5Ah) The W25Q16CL features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified but more may be added in the future ...
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... Supports Quad Input Quad Output =1 Supports Dual Input Dual Output =1 Dual Transfer Rate not Supported =0 3-Byte/24-Bit Addressing Supports Single Input Dual Output = W25Q16CL COMMENT SFDP Signature = 50444653h SFDP revision 1.1 1 Parameter Header EFh = Winbond Serial Flash Basics Revision 1.0 (2) 4 Dwords ...
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... Dummy Bits are needed No Mode Bits are needed 8 Dummy Bits are needed No Mode Bits are needed 8 Dummy Bits are needed 8 Mode bits are needed No Dummy bits are needed - 58 - W25Q16CL 16 Mega Bits = 00FFFFFFh Fast Read Quad I/O Setting Fast Read Quad Output Setting ...
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... Erase Security Registers (44h) The W25Q16CL offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Instruction (42h) Figure 36. Program Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h W25Q16CL A11-8 A7 Byte Address Byte Address Byte Address ...
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... Instruction (48h) Instruction (48h) Figure 37. Read Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h Publication Release Date: July 08, 2010 - 61 - W25Q16CL A11-8 A7 Byte Address Byte Address Byte Address Preliminary - Revision A ...
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... Electrostatic Discharge Voltage Notes: 1. Specification for W25Q16CL is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
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... Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t 10 (1) VSL t 1 (1) PUW V 1.0 (1) WI Figure 38. Power-up Timing and Voltage Levels - 63 - W25Q16CL SPEC UNIT MAX µ 2.0 V Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC VCC x 0 100 µ –100 µA VCC – 0 W25Q16CL SPEC UNIT TYP MAX ±2 µA ±2 µ µ µA 4/5/6 6/7.5/9 ...
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... Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL MIN 0.2 VCC to 0.8 VCC IN 0.3 VCC to 0.7 VCC IN O 0.5 VCC to 0.5 VCC UT Figure 39. AC Measurement I/O Waveform - 65 - W25Q16CL SPEC UNIT MAX Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... DH t CHSH t SHCH Array Read SHSL CSH Read t t SHSL 2 CSH ( SHQZ DIS t t CLQV t t CLQX HO t HLCH - 66 - W25Q16CL SPEC MIN TYP MAX 0.1 0 100 Continued – next page ...
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... RES (2) t SUS t W (4) t BP1 (4) t BP2 BPN BP1 + BP2 * W25Q16CL SPEC ALT MIN TYP MAX 100 2 200/400 120 800 150 ...
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... Serial Output Timing 12.9 Serial Input Timing 12.10 Hold Timing - 68 - W25Q16CL ...
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... MILLIMETERS Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 3.80 4.00 4.80 5.00 1.27 BSC 5.80 6.20 --- 0.10 0.40 1.27 0° 10° W25Q16CL θ θ 0.25 0.25 GAUGE PLANE GAUGE PLANE INCHES Min Max 0.053 0.069 0.004 0.010 0.013 0.020 0.008 0.010 0.150 0.157 0.188 0.196 0.050 BSC 0.228 0.244 --- 0.004 0.016 0.050 0° ...
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... BSC. 7.90 8.10 0.303 0.65 0.80 0.020 --- 0.10 --- --- 8° 0° W25Q16CL GAUGE PLANE GAUGE PLANE INCHES Nom Max 0.077 0.085 0.006 0.010 0.071 0.075 0.017 0.019 0.008 0.010 0.208 0.212 0.206 0.210 0.208 0.212 0.206 0.210 0.050 BSC. 0.311 0.319 0.026 ...
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... MILLIMETERS Nom Max Min --- 5.33 --- --- --- 0.015 3.30 3.43 0.125 9.27 10.16 0.355 7.62 BSC. 6.35 6.48 0.245 3.30 3.81 0.115 9.02 9.53 0.335 7° 15° 0° W25Q16CL INCHES Nom Max --- 0.210 --- --- 0.130 0.135 0.365 0.400 0.300 BSC. 0.250 0.255 0.130 0.150 0.355 0.375 7° 15° Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... MILLIMETERS Nom Max Min 0.75 0.80 0.028 0.02 0.05 0.000 0.40 0.48 0.014 0.20 REF. --- --- 6.00 6.10 0.232 3.40 3.45 0.132 5.00 5.10 0.193 4.30 4.35 0.167 1.27 BSC. 0.60 0.65 0.022 --- 0.075 0.000 - 72 - W25Q16CL INCHES Nom Max 0.030 0.031 0.001 0.002 0.016 0.019 0.008 REF. --- 0.236 0.240 0.134 0.136 0.197 0.201 0.169 0.171 0.050 BSC. 0.024 0.026 --- 0.003 ...
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... The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. MILLIMETERS Min Nom Max SOLDER PATTERN 3.40 4.30 6.00 0.50 0. W25Q16CL INCHES Min Nom Max 0.134 0.169 0.236 0.020 0.026 Publication Release Date: July 08, 2010 Preliminary - Revision A ...
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... BSC. 0.81 1.27 0.015 --- 0.076 --- --- 8° 0° W25Q16CL GAUGE PLANE GAUGE PLANE DETAIL A DETAIL A INCHES Nom Max 0.098 0.104 --- 0.012 0.091 --- 0.016 0.020 0.009 0.011 0.406 0.413 0.406 0.419 0.295 0.299 0.050 BSC. 0.032 0.050 --- ...
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... Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 4. For shipments with OTP feature enabled, please specify when placing orders. ( 8-pad WSON 6x5mm DA = 8-pin PDIP 300-mil - 75 - W25Q16CL (2) 25Q 16C 16-pin SOIC 300-mil ...
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... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q16CL SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE New Create Preliminary Important Notice - 77 - W25Q16CL DESCRIPTION Publication Release Date: July 08, 2010 Preliminary - Revision A ...