w25q40bw Winbond Electronics Corp America, w25q40bw Datasheet
w25q40bw
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w25q40bw Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI W25Q40BW Publication Release Date: January 27, 2011 - 1 - Preliminary - Revision A ...
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... Erase/Program Suspend Status (SUS) ................................................................................ 12 8.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) ................................................................ 12 8.1.10 Quad Enable (QE) .............................................................................................................. 13 8.1.11 Status Register Memory Protection (CMP = 0) ................................................................... 14 8.1.12 Status Register Memory Protection (CMP = 1) ................................................................... 15 8.2 INSTRUCTIONS ................................................................................................................. 16 8.2.1 Manufacturer and Device Identification ................................................................................ 16 8.2.2 Instruction Set Table 1 (Erase, Program Instructions) .......................................................... 17 Table of Contents - 2 - W25Q40BW ...
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... Read Unique ID Number (4Bh) ........................................................................................... 52 8.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 53 8.2.36 Erase Security Registers (44h) ........................................................................................... 54 8.2.37 Program Security Registers (42h) ...................................................................................... 55 8.2.38 Read Security Registers (48h) ............................................................................................ 56 9. ELECTRICAL CHARACTERISTICS .............................................................................................. 57 9.1 Absolute Maximum Ratings ................................................................................................ 57 9.2 Operating Ranges .............................................................................................................. 57 9.3 Power-up Timing and Write Inhibit Threshold .................................................................... 58 W25Q40BW Publication Release Date: January 27, 2011 - 3 - Preliminary - Revision A ...
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... Serial Output Timing ........................................................................................................... 63 9.9 Serial Input Timing .............................................................................................................. 63 9.10 Hold Timing ........................................................................................................................ 63 10. PACKAGE SPECIFICATION .......................................................................................................... 64 10.1 8-Pin SOIC 150-mil (Package Code SN) ........................................................................... 64 10.2 8-Pad 6x5mm WSON (Package Code ZP) ........................................................................ 65 10.3 8-Pad USON 2x3-mm (Package Code UX) ....................................................................... 67 11. ORDERING INFORMATION .......................................................................................................... 68 11.1 Valid Part Numbers and Top Side Marking ........................................................................ 69 12. REVISION HISTORY ...................................................................................................................... W25Q40BW ...
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... Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q40BW has 128 erasable sectors and 8 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... PIN CONFIGURATION SOIC 150-MIL Figure 1a. W25Q40BW Pin Assignments, 8-pin SOIC 150-mil (Package Code SN) 4. PAD CONFIGURATION WSON 6X5-MM, USON 2X3-MM Figure 1b. W25Q40BW Pad Assignments, 8-pad WSON 6x5-mm, USON 2x3-mm (Package Code ZP & UX) 5. PIN DESCRIPTION SOIC 150-MIL, WSON 6X5-MM & USON 2X3-MM PIN NO. ...
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... Package Types W25Q40BW is offered in an 8-pin plastic 150-mil width SOIC (package code SN), 6x5-mm WSON (package code ZP) and 2x3-mm USON (package code UX) as shown in figure 1a, and 1b, respectively. Package diagrams and dimensions are illustrated at the end of this datasheet. 5.2 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance ...
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... SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q40BW Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh ...
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... Dual SPI Instructions The W25Q40BW supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP) ...
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... One Time Program (OTP) write protection * Note: This feature is available upon special order. Please contact Winbond for details. Upon power- power-down, the W25Q40BW will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 37). While reset, all WI operations are disabled and no instructions are recognized ...
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... The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. Publication Release Date: January 27, 2011 - 11 - W25Q40BW , and ...
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... When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again until the next power-down, power-up cycle. Status Register is permanently protected and can not be (2) written to W25Q40BW (1) ...
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... S14 S13 S13 S12 S12 S11 S11 SUS SUS CMP CMP LB3 LB3 LB2 LB2 LB1 LB1 Figure 3b. Status Register-2 Publication Release Date: January 27, 2011 - 13 - W25Q40BW BP0 BP0 WEL BUSY WEL BUSY S10 S10 LB0 LB0 QE ...
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... Note don’t care W25Q40BW (4M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 7 070000h – 07FFFFh 6 and 7 060000h – 07FFFFh 4 thru 7 040000h – 07FFFFh 0 000000h – 00FFFFh 0 and 1 000000h – 01FFFFh 0 thru 3 000000h – 03FFFFh 0 thru 7 000000h – ...
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... Note don’t care W25Q40BW (4M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES 0 thru 7 000000h – 07FFFFh 0 thru 6 000000h – 06FFFFh 0 thru 5 000000h – 05FFFFh 0 thru 3 000000h – 03FFFFh 1 thru 7 010000h – 07FFFFh 2 thru 7 020000h – 07FFFFh 4 thru 7 040000h – ...
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... INSTRUCTIONS The instruction set of the W25Q40BW consists of thirty four basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 FFh Publication Release Date: January 27, 2011 - 17 - W25Q40BW BYTE 5 BYTE 6 A7–A0 D7–D0 (3) A7–A0 D7–D0, … A7–A0 A7–A0 A7–A0 Preliminary - Revision A ...
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... A23-A0, M7-M0 (x,x, D7-D0, …) (4) (3) A23-A0, M7-M0 (D7-D0, …) (4) xxxxxx, W6-W4 Set Burst with Wrap Input IO0 = W4, x IO1 = W5, x IO2 = IO3 = W25Q40BW BYTE 4 BYTE 5 BYTE 6 A7-A0 (D7-D0) A7-A0 dummy (D7-D0) A7-A0 dummy (D7-D0, …) A7-A0 dummy (D7-D0, …) (1) (D7-D0, … ...
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... A23-A8 A7-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15– W25Q40BW BYTE 4 BYTE 5 BYTE 6 (1) dummy (ID7-ID0) 00h (MF7-MF0) (ID7-ID0) (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) (ID7-ID0) Capacity dummy dummy (ID63-ID0) A7–A0 A7–A0 D7-D0 A7– ...
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... Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit only valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram Figure 4. Write Enable Instruction Sequence Diagram Instruction (50h W25Q40BW ...
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... Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions. Write Disable instruction can also be used to invalidate the Write Enable for Volatile Status Register instruction. Figure 6. Write Disable Instruction Sequence Diagram - 21 - W25Q40BW Publication Release Date: January 27, 2011 Preliminary - Revision A ...
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... However, SRP1 and LB3, LB2, LB1, LB0 can not be changed from “1” to “0” because of the OTP protection for these bits. Upon power off, the volatile Status Register bit values will be lost, and the non- volatile Status Register bit values will be restored when power on again W25Q40BW ...
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... Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. Figure 8. Write Status Register Instruction Sequence Diagram W Status Register 2 Status Register 2 Status Register 2 Status Register 1 Status Register Publication Release Date: January 27, 2011 - 23 - W25Q40BW (See AC Characteristics). (See AC SHSL2 Preliminary - Revision A ...
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... The Read Data instruction sequence is shown in figure Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 9. Read Data Instruction Sequence Diagram - 24 - W25Q40BW R ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 10. Fast Read Instruction Sequence Diagram - 25 - W25Q40BW Publication Release Date: January 27, 2011 Preliminary - Revision A ...
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... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 11. Fast Read Dual Output Instruction Sequence Diagram and IO . This allows data to be transferred from the W25Q40BW pin should be high-impedance prior to the falling edge of the first data 0 ...
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... Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q40BW at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of F Electrical Characteristics). This is accomplished by adding eight “ ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 8.2.20 for detail descriptions). Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 ≠ 10 W25Q40BW ...
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... Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: January 27, 2011 - 29 - W25Q40BW Preliminary - Revision A ...
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... A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 8.2.20 for detail descriptions). Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5 The Quad I/O dramatically reduces instruction overhead . - 30 - W25Q40BW and IO and four Dummy 2 3 Byte 1 Byte 1 Byte 2 Byte 2 ≠ ...
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... The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 8.2.18 for detail descriptions. Publication Release Date: January 27, 2011 - 31 - W25Q40BW Preliminary - Revision A ...
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... Figure 15a. Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5 Byte 1 Byte 1 Byte 2 Byte 2 ≠ W25Q40BW ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Publication Release Date: January 27, 2011 - 33 - W25Q40BW Preliminary - Revision A ...
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... Byte 2 Byte 2 Byte 3 Byte 3 Byte 1 Byte W25Q40BW Byte 4 Byte 4 ≠ ...
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... Byte 4 Byte 4 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Publication Release Date: January 27, 2011 - 35 - W25Q40BW Preliminary - Revision A ...
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... Wrap instruction should be issued to set The default value of W4 upon power the case of a system Reset while recommended that the controller issues a Set Burst with Wrap instruction to reset prior to any normal Read instructions since W25Q40BW does not have a hardware Reset Pin. ...
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... Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O Since W25Q40BW does not have a hardware Reset pin the controller resets while W25Q40BW is set to Continuous Mode Read, the W25Q40BW will not recognize any initial standard SPI instructions from the controller. To address this possibility recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. Figure 19. Page Program Instruction Sequence Diagram - 38 - W25Q40BW ...
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... Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 20. Figure 20. Quad Input Page Program Instruction Sequence Diagram , and IO . The Quad Page Program can Publication Release Date: January 27, 2011 - 39 - W25Q40BW Preliminary - Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Sector Erase SE Figure 21. Sector Erase Instruction Sequence Diagram - 40 - W25Q40BW ...
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... Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 22. 32KB Block Erase Instruction Sequence Diagram 1 (See AC Characteristics). While the Block Erase BE Publication Release Date: January 27, 2011 - 41 - W25Q40BW Preliminary - Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 23. 64KB Block Erase Instruction Sequence Diagram (See AC Characteristics). While the Block Erase cycle W25Q40BW ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 24. Chip Erase Instruction Sequence Diagram - 43 - W25Q40BW Publication Release Date: January 27, 2011 Preliminary - Revision A ...
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... It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. Figure 25. Erase/Program Suspend Instruction Sequence ” (See AC Characteristics) is required SUS ” following the preceding SUS - 44 - W25Q40BW ...
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... Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “t Figure 26. Erase/Program Resume Instruction Sequence ” following a previous Resume instruction. SUS Publication Release Date: January 27, 2011 - 45 - W25Q40BW Preliminary - Revision A ...
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... This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 27. Deep Power-down Instruction Sequence Diagram - 46 - W25Q40BW ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28a. The Device ID values for the W25Q40BW is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
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... Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram - 48 - W25Q40BW ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 29. The Device ID values for the W25Q40BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... CLK with most significant bits (MSB) first as shown in figure 30. The Device ID values for the W25Q40BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 31. The Device ID values for the W25Q40BW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q40BW device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the W25Q40BW provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Erase Security Registers (44h) The W25Q40BW offers four 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1) ...
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... Figure 35. Program Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h 00h Publication Release Date: January 27, 2011 - 55 - W25Q40BW A11-8 A7 Byte Address Byte Address Byte Address Byte Address Preliminary - Revision A ...
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... Instruction (48h) Instruction (48h) Figure 36. Read Security Registers Instruction Sequence A23-16 A15-12 00h 00h 00h 00h W25Q40BW A11-8 A7 Byte Address Byte Address Byte Address Byte Address ...
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... Electrostatic Discharge Voltage Notes: 1. Specification for W25Q40BW is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
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... Power-up Timing and Write Inhibit Threshold Parameter VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. Symbol t (1) VSL t (1) PUW V (1) WI Figure 37. Power-up Timing and Voltage Levels - 58 - W25Q40BW spec MIN MAX 1.0 1.4 Unit µ ...
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... DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC –0.5 VCC x 0 100 µ –100 µA VCC – 0.2 OH Publication Release Date: January 27, 2011 - 59 - W25Q40BW SPEC UNIT TYP MAX ±2 µA ±2 µ µ µA 4/5/6 ...
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... Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL Figure 38. AC Measurement I/O Waveform - 60 - W25Q40BW SPEC UNIT MIN MAX 0.2 VCC to 0.8 VCC V 0.3 VCC to 0.7 VCC V 0.5 VCC to 0.5 VCC V ...
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... SHSL 1 CSH Read SHSL CSH ( SHQZ DIS CLQV CLQV CLQX HO t HLCH Publication Release Date: January 27, 2011 - 61 - W25Q40BW SPEC UNIT MIN TYP MAX D.C. 80 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ ...
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... RES (2) t SUS BP1 (4) t BP2 (typical) and BPN BP1 + BP2 * W25Q40BW SPEC UNIT TYP MAX µs 30 µs 30 µs 20 µ µs 2.5 10 µs 0.4 0.8 ms (5) 30 ...
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... Serial Output Timing 9.9 Serial Input Timing 9.10 Hold Timing Publication Release Date: January 27, 2011 - 63 - W25Q40BW Preliminary - Revision A ...
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... MILLIMETERS Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 3.80 4.00 4.80 5.00 1.27 BSC 5.80 6.20 --- 0.10 0.40 1.27 0° 10° W25Q40BW θ θ 0.25 0.25 GAUGE PLANE GAUGE PLANE INCHES Min Max 0.053 0.069 0.004 0.010 0.013 0.020 0.008 0.010 0.150 0.157 0.188 0.196 0.050 BSC 0.228 0.244 --- 0.004 0.016 0.050 0° ...
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... REF. --- --- 6.00 6.10 0.232 3.40 3.45 0.132 5.00 5.10 0.193 4.30 4.35 0.167 1.27 BSC. 0.60 0.65 0.022 --- 0.075 0.000 Publication Release Date: January 27, 2011 - 65 - W25Q40BW INCHES Nom Max 0.030 0.031 0.001 0.002 0.016 0.019 0.008 REF. --- 0.236 0.240 0.134 0.136 0.197 0.201 0.169 0.171 0.050 BSC. 0.024 0.026 --- 0.003 Preliminary - Revision A ...
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... Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. MILLIMETERS Min Nom Max SOLDER PATTERN 3.40 4.30 6.00 0.50 0. W25Q40BW INCHES Min Nom Max 0.134 0.169 0.236 0.020 0.026 ...
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... W25Q40BW E L INCHES TYP. MAX 0.022 0.024 0.001 0.002 0.010 0.012 0.006 ― 0.079 0.083 0.063 0.065 0.118 0.122 0.008 0.010 0.020 ― 0.018 0.020 0.004 ― 0.014 0.016 ― ...
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... Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 4. For shipments with OTP feature enabled, please specify when placing orders. ( 8-pad WSON 6x5- W25Q40BW (2) 25Q 40B ...
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... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q40BW SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE New Create Preliminary Important Notice - 70 - W25Q40BW DESCRIPTION ...