cy62168dv30 Cypress Semiconductor Corporation., cy62168dv30 Datasheet

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cy62168dv30

Manufacturer Part Number
cy62168dv30
Description
16-mbit 2m X 8 Mobl Static Ram
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05329 Rev. *F
Features
Functional Description
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
Note:
• Very high speed
• Wide voltage range
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
1. For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
— 55 ns
— 2.2V – 3.6V
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f
package
CE
CE
1
2
[1]
WE
OE
A
A
A
A
A
A
A
A
A
A
A
A
A
11
12
10
1
1
2
9
0
3
4
5
7
8
6
, CE
2
Max
and OE features
(55 ns Speed)
198 Champion Court
Data in Drivers
2048K x 8
DECODER
ARRAY
COLUMN
16-Mbit (2M x 8) MoBL
®
) in
POWER
DOWN
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE
LOW. The input/output pins (I/O
a high-impedance state when: deselected Chip Enable 1
(CE
(OE HIGH), or during a write operation (Chip Enable 1 (CE
LOW and Chip Enable 2 (CE
Writing to the device is accomplished by taking Chip Enable 1
(CE
(WE) input LOW. Data on the eight I/O pins (I/O
is then written into the location specified on the address
pins(A
Reading from the device is accomplished by taking Chip
Enable 1 (CE
Enable 2 (CE
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
LOW and CE
during a write operation (CE
LOW). See the truth table for a complete description of read
and write modes.
1
1
) HIGH or Chip Enable 2 (CE
) LOW and Chip Enable 2 (CE
0
through A
San Jose
2
2
) HIGH while forcing Write Enable (WE) HIGH.
1
HIGH), the outputs are disabled (OE HIGH), or
) and Output Enable (OE) LOW and Chip
20
).
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CY62168DV30 MoBL
0
1
2
3
4
5
6
7
2
1
1
) HIGH and WE LOW).
LOW and CE
) HIGH or Chip Enable 2 (CE
0
0
through I/O
Revised July 27, 2006
2
) LOW, outputs are disabled
through I/O
2
®
) HIGH and Write Enable
Static RAM
7
2
) are placed in a
7
HIGH and WE
) are placed in
0
408-943-2600
through I/O
®
2
1
7
1
)
)
)
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cy62168dv30 Summary of contents

Page 1

... Available in Pb-free and non Pb-free 48-ball VFBGA package [1] Functional Description The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL portable applications such as cellular telephones ...

Page 2

... Operating MHz Speed [3] Max. (ns) Typ. Max. 3 ensure proper operation. ® CY62168DV30 MoBL Power Dissipation (mA Standby I (µA) Max SB2 [3] [3] Typ. Max. Typ. Max 2 25° ...

Page 3

... 3.6V CC Test Conditions T = 25° MHz CC(typ.) (min) and 100 µs wait time after V stabilization ® CY62168DV30 MoBL ......................–0. 0.3V CC(max) Ambient [6] [ –40°C to +85°C 2.2V – 3.6V CY62168DV30-55 [3] Min. Typ. Max. Unit 2 ...

Page 4

... V <0. − 0. > V < 0. DATA RETENTION MODE V V > 1 CC(min) t CDR > 100 µs or stable CC(min.) CC(min.) CY62168DV30 MoBL VFBGA Unit °C/W 55 °C/W 16 90% 10% Fall time Unit Ω Ω Ω V [3] Min. Typ. Max. Unit 1.5 3.6 V µ ...

Page 5

... Test Loads and Waveforms” section less than less than t , and t HZCE LZCE HZOE LZOE = V , and All signals must be ACTIVE to initiate a write and any of these ® CY62168DV30 MoBL 55 ns Min. Max. Unit ...

Page 6

... During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05329 Rev. *F [14, 15 OHA DOE DATA VALID 50 SCE PWE t SD VALID DATA = transition HIGH. 2 ® CY62168DV30 MoBL DATA VALID t HZOE t HZCE HIGH IMPEDANCE 50 Page [+] Feedback ...

Page 7

... SD VALID DATA [19 SCE PWE t SD VALID DATA Inputs/Outputs Deselect/Power-down Deselect/Power-down -I/O ) Read 0 7 -I/O ) Write 0 7 Output Disabled CY62168DV30 MoBL LZWE Mode Power Standby ( Standby ( Active ( Active ( Active ( Page ® ...

Page 8

... Cypress against all charges. Package Package Type Diagram 51-85178 48-ball Fine Pitch BGA ( mm) 48-ball Fine Pitch BGA ( mm) (Pb-free) 48-ball VFBGA ( mm) (51-85178) A ® CY62168DV30 MoBL Operating Range Industrial BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.30±0.05(48X) ...

Page 9

... Document History Page Document Title: CY62168DV30 MoBL Document Number: 38-05329 Issue REV. ECN NO. Date ** 118409 09/30/02 *A 123693 02/05/03 *B 126556 04/24/03 *C 132869 01/15/04 *D 272589 See ECN *E 335864 See ECN *F 492895 See ECN Document #: 38-05329 Rev. *F ® ® , 16-Mbit ( MoBL Static RAM Orig. of Change Description of Change ...

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