74ALVC16721MTD Fairchild Semiconductor, 74ALVC16721MTD Datasheet

74ALVC16721MTD

Manufacturer Part Number

74ALVC16721MTD

Description

IC FLIP FLOP 20BIT D LV 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Type

D-Type Busr

Datasheet

1.74ALVC16721MTD.pdf (6 pages)

Specifications of 74ALVC16721MTD

Function

Standard

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

200MHz

Delay Time - Propagation

1.3ns

Trigger Type

Positive Edge

Current - Output High, Low

24mA, 24mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC16721MTD

74ALVC16721

Low Voltage 20-Bit D-Type Flip-Flops

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16721 contains twenty non-inverting D-type

flip-flops with 3-STATE outputs and is intended for bus ori-

ented applications.

The 74ALVC16721 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC16721 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O compatibility up to 3.6V.

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500691

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

Pin Names

CLK

1.8V–3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

–D

–O

4.0 ns max for 3.0V to 3.6V V

4.9 ns max for 2.3V to 2.7V V

8.8 ns max for 1.65V to 1.95V V

Human body model

Machine model

(CLK to O

Package Description

)

Output Enable Input (Active LOW)

Clock Input

Inputs

Outputs

Clock Enable Input (Active LOW)

supply operation

200V

2000V

through a pull-up resistor; the minimum

October 2001

Revised October 2001

Description

www.fairchildsemi.com

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74ALVC16721MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC16721MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table D –D CLK HIGH Voltage Level L ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-inverting Functions ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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