74ALVC16821MTDX Fairchild Semiconductor, 74ALVC16821MTDX Datasheet
74ALVC16821MTDX
Specifications of 74ALVC16821MTDX
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74ALVC16821MTDX Summary of contents
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... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation Features 1.65V–3.6V V supply operation CC 3.6V tolerant inputs and outputs ...
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Connection Diagram Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com Truth Tables Inputs CLK OE D – ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.3 CLK Output Enable Time 1.3 PZL PZH Output Disable ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...