lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 34

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

RY/BY# mode) will remain low until the reset
operation is complete. Then, the operation will abort
and the device will enter deep power-down. The
aborted operation may leave data partially altered.
Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V
register.
The CUI latches commands issued by system
software and is not altered by V
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power-
down or after V
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V
transitions down to V
in read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration
during power transitions. Upon power-up, the
device is indifferent as to which power supply (V
or V
CUI to read array mode at power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either to V
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = V
state.
CC
) powers-up first. Internal circuitry resets the
CC
CC
voltages above V
IL
regardless of its control inputs
transitions below V
PPLK
, the CUI must be placed
IL
LKO
clear the status
LKO
IH
when V
PP
will inhibit
.
or CE#
PP
PP
PP
is
- 34 -
5.7 Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid-
state storage can consume negligible power by
lowering RP# to V
access is again needed, the devices can be read
following the t
required after RP# is first raised to V
6.2.4 through 6.2.6 "AC CHARACTERISTICS -
READ-ONLY and WRITE OPERATIONS" and
Fig. 15, Fig. 16, Fig. 17 and Fig. 18 for more
information.
PHQV
IL
and t
standby or sleep modes. If
LH28F160S5-L/S5H-L
PHWL
wake-up cycles
IH
. See Section