is24c128-3z Integrated Silicon Solution, Inc., is24c128-3z Datasheet - Page 5

• Manufacturer Part Number: is24c128-3z
• Description: 262,144-bit/131,072-bit 2-wire Serial Cmos Eeprom
• Manufacturer: Integrated Silicon Solution, Inc.

IS24C128-2/3
IS24C256-2/3
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation, the
IS24CXXX initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write
operation. If the IS24CXXX is still busy with the write
operation, no ACK will be returned. If the IS24CXXX has
completed the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
slave address is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24CXXX contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a read or write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24CXXX
receives the Device Addressing Byte with a READ
operation (read/write bit set to “1”), it will respond an
ACKnowledge and transmit the 8-bit data word stored at
address location n+1. The master will not acknowledge
the transfer but does generate a STOP condition and the
IS24CXXX discontinues transmission. If 'n' is the last byte
of the memory, then the data from location '0' will be
transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
Random Address Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a 'dummy'
write operation by sending the START condition, slave
address and word address of the location it wishes to
read. After the IS24CXXX acknowledge the word address,
the Master device resends the START condition and the
slave address, this time with the R/W bit set to one. The
IS24CXXX then responds with its acknowledge and sends
the data requested. The master device does not send an
acknowledge but will generate a STOP condition. (Refer
to Figure 9. Random Address Read Diagram.)
Integrated Silicon Solution, Inc. — www.issi.com —
ADVANCED INFORMATION Rev. 00B
07/02/02
1-800-379-4774
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24CXXX sends initial byte sequence, the master device
now responds with an ACKnowledge indicating it requires
additional data from the IS24CXXX. The IS24CXXX
continues to output data for each ACKnowledge
received. The master device terminates the sequential
READ operation by pulling SDA HIGH (no ACKnowledge)
indicating the last data word to be read, followed by a
STOP condition.
The data output is sequential, with the data from address
n followed by the data from address n+1, ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential read operation. When the memory address
boundary (32767 for IS24C256-2 and IS24C256-3; 16383
for IS24C128-2 and IS24C128-3) is reached, the address
counter “rolls over” to address 0, and the IS24CXXX-2
continues to output data for each ACKnowledge received.
(Refer to Figure 10. Sequential Read Operation Starting
with a Random Address READ Diagram.)
ISSI
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