xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 8

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal
interconnections are established by the configuration data
contained in the FPGA’s bitstream. The bitstream is loaded
into the FPGA either automatically upon power up, or on
command, depending on the state of the FPGA's mode
pins. Xilinx Platform Flash PROMs are designed to
download directly to the FPGA configuration interface.
FPGA configuration modes which are supported by the
XQF32P Platform Flash PROMs include: Master Serial,
Slave Serial, Master SelectMAP, and Slave SelectMAP.
Below is a short summary of the supported FPGA
configuration modes. See the respective FPGA data sheet
for device configuration details, including which
configuration modes are supported by the targeted FPGA
device.
DS541 (v1.0) November 27, 2006
Product Specification
R
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
4 Design Revisions
4 Design Revisions
(16 Mbits)
(16 Mbits)
(16 Mbits)
(16 Mbits)
PROM 0
(8 Mbits)
(8 Mbits)
(8 Mbits)
(8 Mbits)
PROM 0
PROM 1
REV 0
REV 1
REV 2
REV 3
REV 0
REV 1
REV 2
REV 3
(b) Design Revision storage examples spanning two XQF32P PROMs
(a) Design Revision storage examples for a single XQF32P PROM
Figure 4: Design Revision Storage Examples
3 Design Revisions
3 Design Revisions
(16 Mbits)
(16 Mbits)
(16 Mbits)
(32 Mbits)
(8 Mbits)
(8 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 2
REV 0
REV 1
REV 2
www.xilinx.com
(16 Mbits)
(16 Mbits)
(32 Mbits)
(32 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 0
REV 1
2 Design Revisions
2 Design Revisions
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external
memory synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
(24 Mbits)
(16 Mbits)
(16 Mbits)
(32 Mbits)
(8 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 0
REV 1
REV 1
1 Design Revision
1 Design Revision
(32 Mbits)
(32 Mbits)
(32 Mbits)
PROM 0
PROM 0
PROM 1
ds541_04_070906
REV 0
REV 0
REV 0
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