xc5210 Xilinx Corp., xc5210 Datasheet
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xc5210 Summary of contents
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R Preliminary (v1.0) Technical Data XC5200 Logic Cell Array Family April 1995 ...
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R and XACT are registered trademarks of Xilinx. All XC- prefix product designations, XACT-Performance, X-BLOX, XChecker, XDM, LCA, Logic Cell, Express, VersaBlock, and VersaRing are trademarks of Xilinx. The Programmable Logic Company and The Programmable Gate Array Company are service ...
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R Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... XC5204 XC5206 2,200 - 3,900 - 6,000 - 2,700 4,800 7,500 120 196 256 480 784 84 124 148 ® Development System XC5210 XC5215 10,000 - 14,000 - 12,000 18,000 324 484 1,296 1,936 196 244 20 24 ...
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XC5200 Logic Cell Array Family XC5200 Family Compared to XC4000 Family For those readers already familiar with the XC4000 family of Xilinx Field-Programmable Gate Arrays, here is a concise description of the similarities and differences between the XC4000 and XC5200 ...
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Table 3. Routing Resource Comparison Resource XC5200 Single-length Lines 10 Double-length Lines 4 Longlines 8 Direct Connects 8 VersaRing yes • The TLM process allows significant improvements in the routing structure. Each XC5200 VersaBlock element has complete intra-CLB routing, the ...
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XC5200 Logic Cell Array Family CO LC3 LC2 LC1 LC0 LC0 Figure 3. ...
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VersaRing I/O Interface The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do ...
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XC5200 Logic Cell Array Family Development System The powerful features of the XC5200 device family require an equally powerful, yet easy-to-use, set of development tools. Xilinx provides an enhanced version of the Xilinx Automatic CAE Tools (XACT), optimized for the ...
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Design Implementation The design implementation tools satisfy the requirements for an automated design process. Logic partitioning, block placement, and signal routing are performed by the PPR program. The partitioner takes the logic from the entered design and maps the logic ...
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XC5200 Logic Cell Array Family Detailed Functional Description CLB Logic Figure 3 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a D-Type ...
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Carry Function The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol on a schematic is used to indicate the XC5200 carry logic. This symbol represents ...
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XC5200 Logic Cell Array Family Cascade Function Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 7 illustrates how the 4-input function generators can be configured to take advantage of these ...
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Buffers The XC5200 family has four dedicated TBUFs per CLB. The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLB’s output enable (TS) ...
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XC5200 Logic Cell Array Family VersaBlock Routing Local Interconnect Matrix The GRM connects to the VersaBlock via 24 bidirectional ports (M0-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these ...
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To GRM M0-M23 24 4 Global Nets 4 North 4 South 4 East Input 4 West Multiplexers Direct North 4 Feedback 4 Direct West 4 4 Direct South Figure 10. VersaBlock Details OUT CLB 5 3 ...
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XC5200 Logic Cell Array Family General Routing Matrix The General Routing Matrix, shown in Figure 11, provides flexible bidirectional connections to the Local Interconnect Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A ...
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GRM Versa- Block GRM Versa- Block GRM Versa- Block Six Levels of Routing Hierarchy 1 Single-length Lines 2 Double-length Lines 3 Direct Connects 4 Longlines and Global Lines 5 LIM Local Interconnect Matrix Logic Cell Feedthrough 6 Path (Contained within ...
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XC5200 Logic Cell Array Family Global Lines Two pairs of horizontal and vertical global lines provide low-skew clock signals to the CLBs. Global lines are driven by low-skew buffers inside the VersaRing. The global lines provide direct input only to ...
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Configuration Configuration is the process of loading design-specific programming data into one or more LCA devices to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral ...
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... CCLK cycle. An XC5210 in the Express mode, for instance, can be configured in about 2 ms. The Express mode does not support CRC error checking, but does support constant- fi ...
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CCLK INIT D0-D7 Serial Data Out (DOUT) Internal INIT RDY/BUSY CS1 Description CCLK INIT (High) Setup time required DIN Setup time required DIN Hold time required CCLK High time CCLK Low time CCLK Frequency Figure 16. Express ...
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... XC5202 42,448 XC5204 70,736 XC5206 106,320 XC5210 165,520 XC5215 237,776 Bits per Frame = (34 x number of Rows for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 8 error check bits + 4 fill bits + 4 extended write bits Number of Frames = (12 x number of Columns for ...
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Clear Address Registers During this phase the configuration address registers are cleared to ensure that they will contain at most a single token at all times. Prior to memory initialization, the XC5200 device eliminates the possibility of multiple tokens within ...
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XC5200 Logic Cell Array Family Pin Functions During Configuration CONFIGURATION MODE: <M2:M1:M0> SLAVE MASTER-SER SYN.PERIPH <1:1:1> <0:0:0> TDI TDI TCK TCK TMS TMS M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) ...
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Pin Descriptions Permanently Dedicated Pins V cc Eight or more (depending on package type) connections to the nominal +5-V supply voltage. All must be connected. GND Eight or more (depending on package type) connections to ground. All must be connected. ...
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XC5200 Logic Cell Array Family Pin Descriptions LDC Low During Configuration is driven Low until configuration completes available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin. INIT ...
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Absolute Maximum Ratings Symbol Description V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering temperature ( 1/16 ...
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... From clock (CK) to output pad (fast), using direct connect between Q and output (O) From clock (CK) to output pad (slew-limited), using direct connect between Q and output (O) Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. Speed Grade -6 Max Symbol ...
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... I to Longline, while TS is Low; i.e., buffer is constantly active TS going Low to Longline going from floating High or Low to active Low or High TS going High to TBUF going inactive, not driving Longline Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. Speed Grade -6 Max Symbol ...
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... These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be used to assure that direct connects are used. 2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. 3. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. Speed Grade Symbol Device ...
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IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The ...
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... Global Reset Delays (see Note 2) Width (High) Delay from internal GCLR to Q Note: 1. The CLB output delay (T Data In hold-time requirement (T 2. Timing is based upon the XC5210 device. For other devices, see XACT Timing Calculator. Speed Grade -6 Min Max Symbol (ns) (ns ...
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R ...
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XC5200 Logic Cell Array Family R1C1 R1C2 R1C3 R2C1 R3C1 R4C1 R5C1 R6C1 R7C1 Left R8C1 R9C1 R10C1 R11C1 R12C1 R13C1 R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14 KEY: I/O Pad CLB, identified ...
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Left 57 58 R1C1 R2C1 R3C1 R4C1 R5C1 R6C1 ...
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... R17C1 R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 KEY: I/O Pad CLB, identified by R#C# = row and column numbers R#C# Figure 20. XC5210 CLB-to-Pad Relationship Top R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 ...
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... R17C1 71 121 72 122 123 R18C1 73 74 Note: Pad numbers (1, 2, …, 196) refer to die pads, not external device pins. Also see the XC5210 pinout table on pages 38-39. Figure 21. XC5210 CLB-to-Pad Relationship (Detail) Bottom Right R18C1 R1C18 R2C18 R18C2 R3C18 R18C3 ...
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XC5200 Logic Cell Array Family † Pin Description PC84 PQ160 PQ208 VCC 2 142 183 1. I/O (A8) 3 143 184 2. I/O (A9) 4 144 185 3. I/O - 145 186 4. I/O - 146 187 5. I/O - ...
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Pin Description PC84 PQ160 PQ208 77. I 78. I 79. I 80. I 81. I 82. I 83. I ...
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... A8 47. I 48. I GND VCC D10 49. I C10 * Indicates unconnected package pins. XC5210 Pinouts Boundary † Pin Description PC84 Scan Order 50. I/O 212 - 51. I/O 213 111 52. I/O 214 114 53. I/O 215 117 54. I/O 216 123 - 217 126 55. I/O 218 129 56 ...
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... I/O (D4 128 U10 147. I 129 T10 VCC 63 100 130 R10 GND 64 101 131 R9 148. I/O (D3) 65 102 132 T9 XC5210 Pinouts (continued) Boundary † Scan Order Pin Description PC84 93 543 149. I/O (RS) 94 546 150. I/O 95 552 151. I/O 96 555 152. I/O 97 558 153. I/O 98 564 154 ...
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XC5200 Logic Cell Array Family Physical Dimensions Dimensions in Inches Lead Pitch 50 Mil 0.004 – C – 84-Pin Plastic PLCC (PC84) 120 121 160 Pin Dimensions in Millimeters Lead Pitch 0.65 mm 160-Pin Plastic PQFP (PQ160) ...
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Typ S/R 0.890 0.070 Dia Typ R (191 Places Stand-Off Pin (4 Places 0.050 ...
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XC5200 Logic Cell Array Family 0.100 Typ S/R 0.899 Max 0.070 Dia Typ P (223 Places Stand-Off Pin C (4 Places 0.050 X ...
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... XC5210 - Commercial = 0 to +70 C Number of Available I/O Pins Max Device I/O PC84 XC5206 148 65 XC5210 196 65 XC5210-6PQ208C Temperature Range Number of Pins Package Type 160 191 208 PLASTIC CERAMIC PLASTIC PQFP PGA PQFP PQ160 PG191 PQ208 ...
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The Programmable Logic Company 2100 Logic Drive, San Jose CA 95124-3400 Tel: (408) 559-7778 Printed in U.S. FAX: (408) 559-7114 0401300 P/N 0401300 E2 ...