XC9500XL Xilinx Corp., XC9500XL Datasheet
XC9500XL
Related parts for XC9500XL
XC9500XL Summary of contents
Page 1
... Superior pin-locking and routability with FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks Table 1: XC9500XL Device Family Macrocells Usable Gates Registers T (ns (ns) SU ...
Page 2
... XC9500XL High-Performance CPLD Family Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated JTAG pins) 44-pin PLCC 44-pin VQFP 48-pin 0.8 mm CSP 64-pin VQFP 100-pin TQFP 144-pin 0.8 mm CSP 144-pin TQFP 208-pin PQFP 256-pin BGA 256-pin FBGA 280-pin 0.8 mm CSP 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR ...
Page 3
... Architecture Description Each XC9500XL device is a subsystem consisting of multi- ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter- connected by the FastCONNECT II switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with extra wide 54inputs and 18 outputs ...
Page 4
... From 54 FastCONNECT II Switch Matrix Macrocell Each XC9500XL macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions control inputs ...
Page 5
... R are initialized to the user-defined preload state (default unspecified). 54 Product Allocator Figure 3: XC9500XL Macrocell Within Function Block All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a product DS054 (v1 ...
Page 6
... XC9500XL High-Performance CPLD Family I/O/GSR I/O/GCK1 I/O/GCK2 I/O/GCK3 Figure 4: Macrocell Clock and Set/Reset Capability 6 Product Term Set Product Term Clock Product Term Reset Global Set/Reset Global Clock 1 Global Clock 2 Global Clock 3 www.xilinx.com 1-800-255-7778 R Macrocell S D DS05404_042101 DS054 (v1.6) January 24, 2002 Preliminary Product Specification ...
Page 7
... PTA DS054 (v1.6) January 24, 2002 Preliminary Product Specification XC9500XL High-Performance CPLD Family Note that the incremental delay affects only the product terms in other macrocells. The timing of the direct product terms is not changed. Macrocell Product Term Logic ...
Page 8
... XC9500XL High-Performance CPLD Family The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 product terms are available to any macrocell, with a maxi- ...
Page 9
... DS054 (v1.6) January 24, 2002 Preliminary Product Specification To Upper Macrocell Product Term Allocator To Lower Macrocell Figure 8: Product Term Allocator Logic www.xilinx.com 1-800-255-7778 XC9500XL High-Performance CPLD Family Product Term Set Global Set/Reset 1 0 D/T CE Global Clocks Product Term Clock Product Term Reset Global Set/Reset Product Term OE ...
Page 10
... XC9500XL High-Performance CPLD Family FastCONNECT II Switch Matrix The FastCONNECT II Switch Matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- FastCONNECT II Switch Matrix 10 sponding to user pin inputs) and all FB outputs drive the FastCONNECT II matrix. Any of these ( fan-in limit of 54) may be selected to drive each FB with a uniform delay. ...
Page 11
... Each output driver is designed to provide fast switching with minimal power noise. All output drivers in the device may be www.xilinx.com 1-800-255-7778 XC9500XL High-Performance CPLD Family I/O Block Bus-Hold User- 1 Programmable Ground ...
Page 12
... GND 2.5V CMOS 2.5V 0V (a) Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems 5V Tolerant I/Os The I/Os on each XC9500XL device are fully 5V tolerant even though the core power supply is 3.3 volts. This allows 5V CMOS signals to connect directly to the XC9500XL inputs without damage. In addition, the 3.3V V supply can be applied before or after 5V signals are applied to the I/Os ...
Page 13
... CCIO 0 PIN Figure 13: Bus-Hold Logic In-System Programming One or more XC9500XL devices can be daisy chained together and programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure ming offers quick and efficient design iterations and elimi- nates package handling. The Xilinx development system ...
Page 14
... Table 3: Data Security Options Default (a) Timing Model The uniformity of the XC9500XL architecture allows a sim- plified timing model for the entire device. The basic timing model, shown in that use the direct product terms only, with standard power setting, and standard slew rate setting. ...
Page 15
... T T SUI PTCK CE T AOI T RAI T PTSR SR T PTTS Macrocell Figure 16: Detailed Timing Model www.xilinx.com 1-800-255-7778 XC9500XL High-Performance CPLD Family Combinatorial D/T Q Logic Setup Time = T Clock to Out Time = T SU (b) Combinatorial D/T Q Logic Internal System Cycle Time = T SYSTEM (d) DS054_15_042101 T SLEW Q T OUT COI ...
Page 16
... Device Outputs Device Inputs and Clocks Function Block JTAG Controller 16 XC9500XL family as well as other CPLD and FPGA fami- lies. The Alliance Series includes CPLD and FPGA implementa- tion technology as well as all necessary libraries and inter- faces for Alliance partner EDA solutions. ...
Page 17
... Included hot socket reference; revised layout; BGA package change for XC95288XL 4/2/99 1.3 Minor typesetting corrections. 6/7/99 1.4 Minor typesetting corrections. 6/7/99 1.5 Added CS280 package 01/25/02 1.6 Added DS054 data sheet number. Added 44-pin VQFP package. Updated Device Family table. DS054 (v1.6) January 24, 2002 Preliminary Product Specification XC9500XL High-Performance CPLD Family Revision www.xilinx.com 1-800-255-7778 17 ...