XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 16

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XL High-Performance CPLD Family
Power-Up Characteristics
The XC9500XL devices are well behaved under all operat-
ing conditions. During power-up each XC9500XL device
employs internal circuitry which keeps the device in the qui-
escent state until the V
(approximately 2.5V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the pins weakly pulled high, as shown in
the supply voltage reaches a safe level, all user registers
become initialized (typically within 200 s), and the device is
immediately available for operation, as shown in
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-up. The JTAG pins are enabled to allow the device
to be programmed at any time. All devices are shipped in
the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
Development System Support
The XC9500XL family and associated in-system program-
ming capabilities are fully supported in either software solu-
tions available from Xilinx.
The Foundation Series is an all-in-one development system
containing schematic entry, HDL (VHDL, Verilog, and
ABEL), and simulation capabilities. It supports the
Table 4: Timing Model Parameters
Table 5: XC9500XL Device Characteristics
16
Notes:
1.
IOB Bus-Hold
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
Parameter
T
SYSTEM
S = the logic span of the function, as defined in the text.
T
T
T
T
T
PSU
PCO
CO
PD
SU
Device Circuitry
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup Time
Product Term Clock-to-output
Internal System Cycle Period
CCINT
Description
supply voltage is at a safe level
Quiescent State
Disabled
Disabled
Disabled
Disabled
Table
Pull-up
Figure
5. When
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17.
Product Term
Allocator
+ T
+ T
+ T
+ T
PTA
PTA
PTA
PTA
-
-
XC9500XL family as well as other CPLD and FPGA fami-
lies.
The Alliance Series includes CPLD and FPGA implementa-
tion technology as well as all necessary libraries and inter-
faces for Alliance partner EDA solutions.
FastFLASH Technology
An advanced 0.35 micron feature size CMOS Flash process is
used to fabricate all XC9500XL devices. The FastFLASH pro-
cess provides high performance logic capability, fast pro-
gramming times, and superior reliability and endurance
ratings.
Erased Device Operation
*
*
*
*
3.8 V
(Typ)
2.5V
(Typ)
0V
S
S
S
S
(1)
Figure 17: Device Behavior During Power-up
Power
V
CCINT
No
Disabled
Disabled
Disabled
Enabled
Pull-up
Quiescent
Low-Power Setting
State
Macrocell
+ T
+ T
+ T
+ T
-
-
LP
LP
LP
LP
Initialization of User Registers
Preliminary Product Specification
User Operation
DS054 (v1.6) January 24, 2002
Valid User Operation
As Configured
As Configured
As Configured
Bus-Hold
Enabled
Slew-Limited
Quiescent
+ T
+ T
+ T
Setting
Output
State
SLEW
SLEW
SLEW
–
-
-
DS054_17_042101
Power
No
R