XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 3

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system pro-
gramming (ISP) and the full IEEE 1149.1 (JTAG) bound-
ary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx Virtex,
Spartan-XL and XC4000XL FPGA families, allowing system
designers to partition logic optimally between fast interface
circuitry and high-density general purpose logic. As shown
in
from 800 to 6400 usable gates with 36 to 288 registers,
respectively. Multiple package options and associated I/O
capacity are shown in
bers are fully pin-compatible, allowing easy design migra-
tion across multiple density options in a given package
footprint.
The XC9500XL architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
DS054 (v1.6) January 24, 2002
Preliminary Product Specification
Table
1, logic density of the XC9500XL devices ranges
R
Table
2. The XC9500XL family mem-
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1-800-255-7778
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V
operation. The XC9500XL device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
times.
Architecture Description
Each XC9500XL device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide
54inputs and 18 outputs. The FastCONNECT II switch
matrix connects all FB outputs and input signals to the FB
inputs. For each FB, up to 18 outputs (depending on pack-
age pin-count) and associated output enable signals drive
directly to the IOBs. See
Function Block
Each Function Block, as shown in
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the FastCONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
XC9500XL High-Performance CPLD Family
Figure 1
Figure 2
is comprised of
3