XC3S1000L Xilinx Corp., XC3S1000L Datasheet
XC3S1000L
Available stocks
Related parts for XC3S1000L
XC3S1000L Summary of contents
Page 1
... Low cost, low power logic solution for high-volume, consumer-oriented applications - Densities as high as 62,000 logic cells Table 1: Summary of Spartan-3L FPGA Attributes Equivalent (One CLB = Four Slices) System Logic Device Gates Cells Rows Columns Total CLBs XC3S1000L 1M 17,280 48 XC3S1500L 1.5M 29,952 64 XC3S4000L 4M 62,208 96 Notes: 1 ...
Page 2
... These elements are organized as shown in of IOBs surrounds a regular array of CLBs. The XC3S1000L and XC3S1500L have two columns of block RAM. The XC3S4000L has four RAM columns. Each column is made up of several 18Kbit RAM blocks; each block is associated with a dedicated multiplier ...
Page 3
R I/O Capabilities The SelectIO feature of Spartan-3L devices provides 18 sin- gle-ended standards and eight differential standards as listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted Table 2: Signal Standards ...
Page 4
... Spartan-3L Low Power FPGA Family Table 3: User I/O and Differential (Diff) I/O Counts FT256 FTG256 Device User Diff XC3S1000L 173 76 XC3S1500L - XC3S4000L - Notes: 1. All Spartan-3L and Spartan-3 devices in the same package are pin-compatible. Package Marking Figure 2 shows the package marking for Spartan-3L FPGAs. The markings on the Spartan-3L package are similar to those on the Spartan-3 package. The ‘ ...
Page 5
... Pb-Free Packaging For additional information on Pb-free packaging, see Packages. Example: XC3S1500L -4 FG Device Type Speed Grade Package Type Device Speed Grade XC3S1000L –4 XC3S1500L XC3S4000L DS313 (v1.2) April 18, 2008 Product Specification XC3S1500L -4 FG 676 C Temperature Range Commercial (T Number of Pins : Implementation and Solder Reflow Guidelines for Pb-Free ...
Page 6
Spartan-3L Low Power FPGA Family Functional Description The Spartan-3L FPGA family is identical to the Spartan-3 FPGA family with respect to device function. See the func- tional description in Module 2 of the Spartan-3 data sheet ( ) for more ...
Page 7
R Power Control PROG_B I/Os V CCINT V CCAUX V (Banks CCO INIT_B DONE CCLK Notes: 1. See Special Considerations, page 8 DS313 (v1.2) April 18, 2008 Product Specification V CCO Supply 2.5V 1. CCAUX ...
Page 8
Spartan-3L Low Power FPGA Family Figure 4, page 7 shows the waveforms for entering and exit- ing the Hibernate mode. The steps for entering the Hibernate mode are as follows: 1. Pull the PROG_B pin Low to put all I/Os ...
Page 9
... Maximum values are the production test limits measured for each device at CCAUX = 3.45V, and V = 2.625V. The FPGA is programmed with a "blank" configuration CCO CCAUX provides quick, approximate, typical estimates, and does not require Device XC3S1000L XC3S1500L XC3S4000L values 85°C with V (all banks) = 3.45V CCO www ...
Page 10
Spartan-3L Low Power FPGA Family Pinout Descriptions Spartan-3L and Spartan-3 devices that correspond in den- sity and package have the same pinout. See the Pinout Related Documentation This data sheet only specifies how the Spartan-3L family differs from the Spartan-3 ...