XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 4

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XL High-Performance CPLD Family
the 90 available, can be allocated to each macrocell by the
product term allocator.
Macrocell
Each XC9500XL macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
4
FastCONNECT II
Switch Matrix
From
54
Figure
Programmable
AND-Array
Figure 2: XC9500XL Function Block
3.
www.xilinx.com
Allocators
1-800-255-7778
Product
Term
Set/Reset
including clock, clock enable, set/reset, and output enable.
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
Global
Macrocell 18
1
Macrocell 1
Clocks
Global
3
18
18
18
Preliminary Product Specification
DS054 (v1.6) January 24, 2002
OUT
PTOE
To FastCONNECT II
Switch Matrix
To I/O Blocks
DS054_02_042101
R