XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 11

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
The input buffer is compatible with 5V CMOS, 5V TTL, 3.3V
CMOS, and 2.5V CMOS signals. The input buffer uses the
internal 3.3V voltage supply (V
input thresholds are constant and do not vary with the
V
DS054 (v1.6) January 24, 2002
Preliminary Product Specification
CCIO
voltage. Each input buffer provides input hysteresis
Macrocell
(Inversion in
AND-array)
R
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
Product Term OE
To FastCONNECT
Switch Matrix
CCINT
Figure 10: I/O Block and Output Enable Capability
Global OE 4
Global OE 3
Global OE 1
Global OE 2
) to ensure that the
PTOE
OUT
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buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See
details.
(50 mV typical) to help reduce system noise for input signals
with slow rise or fall edges.
Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
Macrocells
To other
1
0
XC9500XL High-Performance CPLD Family
Available in XC95144XL
and XC95288XL
Slew Rate
Control
Programmable
Ground
User-
Bus-Hold
I/O Block
DS054_10_042101
I/O
Figure 10
for
11