XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 12

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XL High-Performance CPLD Family
configured for driving either 3.3V CMOS levels (which are
compatible with 5V TTL levels as well) or 2.5V CMOS levels
by connecting the device output voltage supply (V
3.3V or 2.5V voltage supply.
XC9500XL device can be used in 3.3V only systems and
mixed voltage systems with any combination of 5V, 3.3V
and 2.5V power supplies.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of t
under user control. See
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1,” or always
“0.” There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximal design flexibility.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
voltage state, as well as provide for additional device
5V Tolerant I/Os
The I/Os on each XC9500XL device are fully 5V tolerant
even though the core power supply is 3.3 volts. This allows
5V CMOS signals to connect directly to the XC9500XL
inputs without damage. In addition, the 3.3V V
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
ply (V
makes the XC9500XL devices immune to power supply
sequencing problems.
12
5V CMOS
5V TTL or
3.3V CMOS or
2.5V CMOS
CCIO
3.3V
2.5V
) may have power applied in any order. This
5V
0V
5V
0V
0V
0V
Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems
IN
Figure
V
CCINT
3.3V
CCINT
XC9500XL
CPLD
GND
(a)
), and the output power sup-
12.
Figure 11
V
CCIO
OUT
shows how the
3.3V CMOS, 5V TTL
CCINT
3.3V
0V
CCIO
power
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) to a
)
5V CMOS
5V TTL or
3.3V CMOS or
2.5V CMOS
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
Each IOB also provides for bus-hold circuitry (also called a
“keeper”)that is active during valid user operation. The
bus-hold feature eliminates the need to tie unused pins
either high or low by holding the last known state of the input
until the next input signal is present. The bus-hold circuit
drives back the same state via a nominal resistance (R
of 50k ohms. See
drive no higher than V
when interfacing to 2.5V components.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50k ohm pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1k ohm) may be externally
added to any pin to override the default R
force a low state during power-up or any of these other
modes.
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using these devices.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.
3.3V
2.5V
5V
5V
0V
0V
0V
0V
IN
V
Figure
3.3V
CCINT
XC9500XL
CPLD
CCIO
GND
(b)
13. Note the bus-hold output will
Preliminary Product Specification
V
2.5V
to prevent overdriving signals
CCIO
OUT
DS054 (v1.6) January 24, 2002
2.5V CMOS
BH
DS054_11_042101
2.5V
resistance to
0V
BH
R
)