lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 22

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

www.national.com
Operation Descriptions
General
The LM2633 is a combination of three voltage regulator
controllers. Among them, two are switching regulator control-
lers and one is a linear regulator controller. The two switch-
ing controllers, Channel 1 and Channel 2, operate 180˚ out
of phase. They can be independently enabled and disabled.
The linear controller, or Channel 3, is disabled only when
both switching channels are disabled. Channel 1 output
voltage is set by an internal DAC, which accepts a 5-bit VID
code from pins 6 through 10. Channels 2 and 3 output
voltages are adjusted with a voltage divider. Both switching
channels are synchronous and employ peak current mode
control scheme. Protection features include over-voltage
protection (Ch1 and 2), under-voltage protection (all chan-
nels), and positive and negative peak current limit (Ch1 and
2). UVP function can be delayed by an arbitrary amount of
time. Input voltage to the switching regulators can range
from 4.5V to 30V. The linear controller can generate a maxi-
mum 3.8V gate/base drive voltage. With an external NPN
transistor, output voltage can go up to 3.0V. The power good
function always monitors all three output voltages.
Soft Start
If the ON/SSx pin is connected to ground instead of to a
capacitor, the corresponding channel is turned off and will
not start up.
Assume the ON/SSx pin is connected to a capacitor and the
rest of the circuit is set up correctly. When the input voltage
rises above the 4.2V threshold, the internal circuitry is pow-
ered on, the ON/SSx pin should be already held at 1.1V, and
a 2µA current starts to charge the capacitor connected be-
tween the ON/SSx pin and ground. When the ON/SSx pin
voltage exceeds 1.2V, the corresponding channel is turned
on. A MIN_ON_TIME comparator generates the soft start
PWM pulses. As the ON/SSx pin voltage ramps up, the duty
cycle grows, causing the output voltage to ramp up. During
this time, the error amplifier output voltage is clamped at
0.8V, and the duty cycle generated by the PWM comparator
is ignored. When the corresponding output voltage exceeds
99% of the set target voltage, the mode of the channel
transitions from soft start to operating. As a result, the high
clamp at the output of the error amplifier is switched to 2V.
Beyond this point, once the PWM pulses generated by the
PWM comparator are wider than that generated by the MI-
N_ON_TIME comparator, the PWM comparator takes over
and starts to regulate the output voltage. That is, peak
current mode control now takes place.
The speed at which the duty cycle grows depends on the
capacitance of the soft start capacitor. The higher the ca-
pacitance, the slower the speed. However, that speed is
independent of how fast the input voltage rises. That is
because the ramp signal used to generate the soft start duty
cycle has a slope proportional to input voltage, making the
product of duty cycle and input voltage a value that is inde-
pendent of input voltage. This feature makes the soft start
process more predictable and reliable because whether the
input power supply goes through a soft start process or is
applied abruptly does not affect the LM2633 soft start.
During soft start, under-voltage protection is disabled. But
over-voltage protection and current limit are in place.
22
When the ON/SSx pin voltage exceeds 3.5V, a soft start time
out signal (sstox) will be issued. This signal enables the
under-voltage protection. See the Under-Voltage Protection
section.
Shutdown Mode
If both ON/SSx pins are pulled low, the IC will be in shut
down mode. Both top gate-drives of the two switching chan-
nels are turned off while both bottom gate-drives remain on.
The linear channel is also disabled.
The same thing happens to the gate drives when the input
voltage is brought below the UVLO threshold.
Turning Off a Switching Channel
A switching channel can be turned off by pulling its ON/SSx
pin below about 1.1V. Upon detecting a low level on ON/SSx
pin, the corresponding top gate-drive will be turned off and
the bottom gate-drive will be turned on.
In a high current application, it may be necessary to take
special measures to make sure that the output voltage does
not go too negative during shutdown. One of those mea-
sures is to add a Schottky diode in parallel with output
capacitors. Another measure is to fine tune the power stage
parameters such as inductance and capacitance values.
Fault State
Whenever the input voltage becomes too low (less than
about 3.9V), or the IC is too hot and enters thermal shut
down mode, a ’fault’ signal will be generated internally. This
signal will discharge the capacitor connected between the
ON/SSx pin and ground with 3 µA of current until the pin
reaches 1.1V. The switching channels will be turned off upon
seeing this signal.
In the fault state, OVP and UVP are disabled and shut down
latch is released.
Force-PWM Mode
This mode applies to both switching channels si-
multaneously. The force-PWM mode is activated by pulling
the FPWM pin to logic low. In this mode, the top FET and the
bottom FET gate signals are always complementary to each
other. The 0-CROSSING / NEGATIVE CURRENT LIMIT
comparator will be set to detect the negative current limit. In
force-PWM mode, the regulator always operates in Continu-
ous Conduction Mode (CCM) and its steady-state duty cycle
(approximately V
The force-PWM mode is good for applications where fixed
switching frequency is required. It also offers the fastest load
transient response.
In force-PWM mode, the top FET has to be turned on for a
minimum of 220ns each cycle. However, when the required
duty cycle is less than the minimum value, the skip compara-
tor will be activated and pulses will be skipped to maintain
regulation.
Skip Comparator
Whenever the COMPx pin voltage goes below the 0.5V
threshold, the PWM cycles will be ’skipped’ until that voltage
again exceeds the threshold.
Pulse-Skip Mode
This mode is activated by pulling the FPWM pin to a
TTL-compatible logic high and applies to both switching
channels simultaneously. In this mode, the 0-CROSSING /
NEGATIVE CURRENT LIMIT comparator detects the bottom
OUT
/ V
IN
) is almost independent of load.