lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 26

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

www.national.com
Output Capacitor Selection
Because the response speed of the regulator is slow com-
pared to a typical CPU load transient, the regulator has to
rely heavily on the output capacitors to handle the load
transient. The initial overshoot or undershoot is caused by
the ESR of the output capacitors. How the output voltage
recovers after that initial excursion depends on how fast the
output inductor current ramps and how large the output
capacitance is. See Figure 3 . If the total combined ESR of
the output capacitors is not low enough, the initial output
voltage excursion will violate the specification, see V
the ESR is low enough, but there is not enough output
capacitance, output voltage will have too much an extra
excursion and travel outside the specification window, before
it returns to its nominal value, see V
During a load transient, the delta output voltage V
changing components. One is the delta voltage across the
ESR ( V
gained charge ( V
For V
and for V
(Continued)
FIGURE 4. Delta Output Voltage Components
r
FIGURE 3. Load Transient Spec. Violation
, the equation is:
r
), the other is the delta voltage caused by the
q
, the equation is:
q
). Both delta voltages change with time.
c2
.
c
20000807
20000808
has two
c1
. If
(1)
(2)
26
The total change in output voltage during such a load tran-
sient is:
From Figure 4 it can be told that V
at some point in time and then it is going to decrease. The
larger the output capacitance is, the earlier the peak will
happen. If the capacitance is large enough, the peak will
occur at the beginning of the transient, i.e., V
monotonically after the transient happens. To find the peak
position, let the derivative of V
The target is to find the capacitance value that will yield, at
t
into the V
following formula is obtained:
Notice it is already assumed the total ESR is no greater than
R
negative value.
There are two scenarios when calculating the C
Figure 5 . One is that R
lutely no room for V
that R
which means t
necessary to differentiate between the two scenarios when
figuring out the C
Allowed transient voltage excursion
The allowed output voltage excursion during a load transient
is:
Example: V
Since the ripple voltage is included in the calculation of
the worst-case load current excursion. That is, the
worst-case load current excursion should be simply I
peak
V
e_s
c_s
, a V
otherwise the term under the square root will be a
, the inductor ripple current should not be included in
e
is smaller than R
c
C
n
FIGURE 5. R
that equals V
expression and equating the latter to V
= 1.35V, % = 7.5%, % = 1.4%, V
peak
min
is greater than zero. However, it is not
q
by the above formula.
, which means t
V
e
c
e_s
e
is equal to R
= V
c_s
= R
so there is some room for V
. By plugging t
e_s
r
c
+ V
go to zero, and the result is:
vs R
c
will reach its peak value
q
peak
e_s
e
<
= 0s. The other is
so there is abso-
R
peak
e_s
c
will decrease
20000813
expression
rip
min
= 20mV
c_s
. See
c_s
, the
(3)
(4)
(5)
(6)
.
q
,