ncp5424adr2 ON Semiconductor, ncp5424adr2 Datasheet - Page 7

• Manufacturer Part Number: ncp5424adr2
• Description: Dual Synchronous Buck Controller With Input Current Sharing
• Manufacturer: ON Semiconductor

supply controller that utilizes the V
synchronous V
controller or a single output converter that draws
programmable amounts of current from two input voltages.
The fixed−frequency architecture, driven from a common
oscillator, ensures a 180
channels.
V
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the DC output voltage. This control scheme
inherently compensates for variation in either line or load
conditions, since the ramp signal is generated from the
output voltage itself. The V
techniques such as voltage mode control, which generates an
artificial ramp, and current mode control, which generates
a ramp using the inductor current.
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch to 0% or 100% duty cycle as required.
inductor, which causes the V
the duty cycle. Since any variation in inductor current modifies
the ramp signal, as in current mode control, the V
scheme offers the same advantages in line transient response.
modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
COMP
2
The NCP5424 is a dual output or single two−phase power
The V
The V
A variation in line voltage changes the current ramp in the
A variation in load current will affect the output voltage,
Control Method
Figure 3. V
2
2
control method is illustrated in Figure 3. The
method of control uses a ramp signal that is
Compensation
2
RAMP
THEORY OF OPERATION
2
buck regulators can be built using a single
Slope
Control with Slope Compensation
Signal
Error
−
+
PWM
2
2
method differs from traditional
control scheme to compensate
phase differential between
Amplifier
Error
GATE(H)
GATE(L)
2
control method. Two
−
+
APPLICATIONS INFORMATION
Reference
Output
Voltage
V
Voltage
2
FB
control
http://onsemi.com
NCP5424
7
time to the output load step is not related to the crossover
frequency of the error signal loop.
since the transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.
there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
a change in the error signal. The V
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity particularly at higher duty cycle (above 50%).
Start Up
function, which is implemented through the Error Amplifier
and the external Compensation Capacitor. This feature
prevents stress to the power components and overshoot of
the output voltage during start−up. As power is applied to the
regulator, the NCP5424 Undervoltage Lockout circuit
(UVL) monitors the IC’s supply voltage (V
circuit resets an internal fault latch when the input voltage
exceeds 8.6 volts. This fault latch disables the error
amplifiers until it is reset. Once the amplifiers are enabled,
they start charging the compensation capacitors with a 30 uA
constant current that causes a linear voltage ramp. The
output of the error amplifier is connected internally to the
negative input of the PWM comparator. The comparator’s
positive input is connected back to the feedback voltage pin
through a 0.45−volt offset. With the feedback voltage
starting at zero, the offset voltage forces the comparator
high, which prevents resetting the RS latches that control the
output drivers. Once the compensation capacitor voltage
reaches 0.45 volts, the PWM comparator will switch and
The error signal loop can have a low crossover frequency,
Line and load regulation is drastically improved because
The stringent load transient requirements of modern
The NCP5424 features a programmable Soft−Start
2
method of control
CC
). The UVL