lm5041bsdx National Semiconductor Corporation, lm5041bsdx Datasheet - Page 3

• Manufacturer Part Number: lm5041bsdx
• Description: Cascaded Pwm Controller
• Manufacturer: National Semiconductor Corporation

LLP DAP
Pin #
12
13
14
15
16
RT / SYNC
Name
UVLO
TIME
SUB
Pin
CS
SS
Current sense input
Soft-Start control
Push-Pull overlap and
dead time control
Oscillator timing
resistor pin and sync
Line Under-Voltage
Shutdown
Die substrate
Description
Pin
Current sense input to the PWM comparator (current mode control). There is a 50 ns
leading edge blanking on this pin. If CS exceeds 0.5V, the PWM controller will go into
cycle by cycle current limit.
An external capacitor and an internal 10 µA current source, set the soft-start ramp.
Both HD and LD will be forced to a low state if the SS pin is below the shutdown
threshold of 0.45V.
An external resistor (R
A resistor connected between TIME and GND produces overlap. A resistor connected
between TIME and REF produces dead time.
An external resistor sets the oscillator frequency. This pin will also accept an external
oscillator.
An external divider from the power source sets the shutdown levels. Threshold of
operation equals 2.5V. Hysteresis is set by a switched internal current source (20 µA).
The exposed die attach pad of the LLP package should be connected to a PCB
thermal pad at ground potential. For additional information on using National
Semiconductor's No Pull Back LLP package, please refer to Application Note
AN-1187: Leadless Leadframe Package (LLP).
3
SET
) sets the overlap time or dead time for the push-pull outputs.
Pin Application Information
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