bd8203efv-e2 ROHM Co. Ltd., bd8203efv-e2 Datasheet - Page 20

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bd8203efv-e2

Manufacturer Part Number
bd8203efv-e2
Description
5ch System Moter Driver
Manufacturer
ROHM Co. Ltd.
Datasheet
●Notes for use
BD8203EFV
© 2010 ROHM Co., Ltd. All rights reserved.
www.rohm.com
1.Absolute maximum ratings
2.Reverse polarity connection
3.Power supply line
4.GNT line
5.Thermal design
6.Short circuit mode between terminals and wrong mounting
7.Radiation
8.ASO (Area of Safety Operation)
9.TSD (Thermal Shut-Down)
10.Capacitor between output and GNT
11.About the capacitor between the outputs
12. Inspection by the set circuit board
13. Input terminal
14. Earth wiring pattern
We are careful enough for quality control about this IC. So, there is no problem under normal operation, excluding that it exceeds the
absolute maximum ratings. However, this IC might be destroyed when the absolute maximum ratings, such as impressed voltages or the
operating temperature range, is exceeded, and whether the destruction is short circuit mode or open circuit mode cannot be specified.
Please take into consideration the physical countermeasures for safety, such as fusing, if a particular mode that exceeds the absolute
maximum rating is assumed.
Connecting the power line to the IC in reverse polarity (from that recommended) will damage the part. Please utilize the direction
protection device as a diode in the supply line and motor coil line.
Due to return of regenerative current by reverse electromotive force of external coil, using electrolytic and ceramic suppress filter
capacitors (0.1μF) close to the IC power input terminals (Vcc and GNT) are recommended. Please note the electrolytic capacitor value
decreases at lower temperatures and examine to dispense physical measures for safety.
Please keep the SGNT, PGNT,1, PGNT2 line the lowest potential always, and check the GNT voltage when transient voltages are
connected to the IC.
Do not exceed the power dissipation (Pd) of the package specification rating under actual operation, and please design enough
temperature margins. This product has exposed the frame to the back side of the package, but please note that it is assumed to use heat
radiation efficiency by the heat radiation for this part. Please take the heat radiation pattern on not only the surface of the substrate but
also the back of the substrate widely.
Do not mount the IC in the wrong direction and displacement, and be careful about the reverse-connection of the power connector.
Moreover, this IC might be destroyed when the dust short the terminals between them or GNT.
( The outputs of CH1(pin2,3) have NO protection circuit. So please especially be careful about them.)
Strong electromagnetic radiation can cause operation failures.
Do not exceed the maximum ASO and the absolute maximum ratings of the output driver.
The TSD is activated when the junction temperature (Tj) exceeds Tjmax, and the output terminal is switched to OPEN.
The guarantee and protection of set are not purpose. Therefore, please do not use this IC after TSD circuit operates, nor use it for
assumption that operates the TSD circuit.
If a large capacitor is connected between the output and GNT, this IC might be destroyed when Vcc becomes 0V or GNT, because the
electric charge accumulated in the capacitor flows to the output. Please set said capacitor to smaller than 0.1μF.
The output current increases compared with the change between the outputs when the capacitor is connected between the driver outputs.
Therefore, please do measures such as putting bypass capacitor (0.1uF) in a nearest pin of power supply (PVCC) and GNT(PGNT) of this
IC as the route of the output current. Please decide the capacity value after confirming there is no problem in various characteristics
enough, it is possible to pull out capacity at the low temperature happening to the electrolytic capacitor more than the capacity value of the
capacitor between the outputs.
The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge electricity in each
and all process. Moreover, when attaching or detaching from jig in the inspection process, please turn off the power before mounting the
IC, and turn on after mounting the IC, and vice versa. In addition, please take into consideration the countermeasures for electrostatic
damage, such as giving the earth in assembly process, transportation or preservation.
If small signal GNT and large current GNT exist, disperse their pattern. In addition, for voltage change by pattern wiring impedance and
large current not to change voltage of small signal GNT, each ground terminal of IC must be connected at the one point on the set circuit
board. As for GNT of external parts, it is similar to the above-mentioned.
This IC is a monolithic IC, and has P
this P-layer and N-layer of each element. For instance, the resistor or the transistor is connected to the terminal as shown in the figure
below. When the GNT voltage potential is greater than the voltage potential at Terminals A on the resistor, at Terminal B on the transistor,
the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of
surrounding elements close to said parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The
parasitic element operating causes the interference of circuit operation, then the wrong operation and destruction. Therefore, please be
careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GNT (P substrate). Please do not
apply the voltage to the input terminal when the power-supply voltage is not impressed. Moreover, please impress each input terminal
lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage is
impressing.
Terminal-A
Parasitic
element
P
+
+
isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in
GND
P
Resistor
P-Substrate
Example of IC of simple structure
P
+
Terminal-A
Parasitic
element
20/21
Terminal-B
Parasitic
element
P
+
C
B
Transistor(NPN)
E
GND
P
P-Substrate
P
+
GND
Terminal-B
Surrounding
elements
B
C
E
Parasitic
GND
element
Technical Note
2010.02 - Rev.A

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