tle4998s Infineon Technologies Corporation, tle4998s Datasheet - Page 22

• Manufacturer Part Number: tle4998s
• Description: Tle4998s/p-programming Guide
• Manufacturer: Infineon Technologies Corporation

• “DSP stop” should be set prior (as a separate step before switching the DSP off) when
• “PROTOCOL off” should only be set together with “DSP off ”. It can be set if it is
4.2.8
The content of the EEPROM setup registers is shown in
parameters set the sensor hardware, the yellow marked parameters are used by the
DSP algorithms and the magenta/cyan values correspond to the parity setup for the
internal forward error correction (FEC). All parameters are unsigned integer values. The
white areas must not be changed.
Table 10
• The parity P
Application Note
0x1A
ADR
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
reading out the calculated data H_CAL and T_CAL. This allows the DSP to finish the
calculation of the current sample and all values in the RAM are consistent. Normally
the cycle time of the protocol should be waited before the DSP is switched off
completely (“DSP off” =1).
desired to get correct protocol output after “DSP off” and “PROTOCOL off” are cleared
again. Otherwise, correct protocol output is guaranteed only after reset.
even bit positions (bit0=LSB, bit2, bit4, ... bit14) and the parity P
(bit1, bit3, ... bit13) must be odd. The parity P
Parity of each column
IC lock (high locks),
clamping high/ low value
gain setting
offset setting
ID, PC...temp. cal. status
bit, Predivider, TQ value
Bandwidth, Range, TL
value, IC lock (low locks)
precal
precal
precal
precal
precal
EEPROM
Description
EEPROM registers
c
of each column (including the precalibration ranges) must be even for
P
P
P
P
P
P
P
P
P
P
P
1
5
c
l
l
l
l
l
l
l
l
l
l
P
L
H
G - register (bit 14...0)
OS - register (bit 14...0)
ID
BW
(2...0)
precal area - do not modify
precal area - do not modify
precal area - do not modify
precal area - do not modify
precal area - do not modify
1
4
c
P
CH - register (bit 6...0)
1
3
c
P
P
C
1
2
20
c
P
Prediv
(bit 3...0)
R
(1...0)
1
1
c
TLE4998S/P-Programming Guide
c
P
1
0
for the column at bit15 (MSB) must be
c
Interface Access Details - Part III
P
TL - register (bit 8...0)
0
9
c
P
0
8
c
P
TQ - register (bit 7...0)
0
7
Table
c
P
CL - register (bit 6...0)
0
6
c
10. The red marked
P
c
0
5
c
for all odd columns
P
0
4
c
P
0
3
V 1.1, 2008-08
c
P
0
2
c
P
0
1
c
P
L
L
0
0
c