lm5109sdx National Semiconductor Corporation, lm5109sdx Datasheet - Page 7

• Manufacturer Part Number: lm5109sdx
• Description: 100v / 1a Peak Half Bridge Gate Driver
• Manufacturer: National Semiconductor Corporation

Timing Diagram
Layout Considerations
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to
2. To prevent large voltage transients at the drain of the top
3. In order to avoid large negative transients on the switch
4. Grounding Considerations:
the IC, and between V
and HS pins to support high peak currents being drawn
from VDD during turn-on of the external MOSFET.
MOSFET, a low ESR electrolytic capacitor must be con-
nected between MOSFET drain and ground (V
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
is to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and mini-
mize noise issues on the gate terminal of the MOSFET.
The MOSFETs should be placed as close as possible to
the gate driver.
strap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET
body diode. The bootstrap capacitor is recharged on the
cycle-by-cycle basis through the bootstrap diode from
the ground referenced V
charging occurs in a short time interval and involves high
a) The first priority in designing grounding connections
b) The second high current path includes the boot-
DD
and V
DD
bypass capacitor. The re-
SS
pins and between HB
SS
).
FIGURE 3.
7
HS Transient Voltages Below
Ground
The HS node will always be clamped by the body diode of
the lower external FET. In some situations, board resis-
tances and inductances can cause the HS node to tran-
siently swing several volts below ground. The HS node can
swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling
2. HB to HS operating voltage should be 15V or less .
3. A low ESR bypass capacitor between HB to HS as well
peak current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current to flow from the
HB supply possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
as VDD to VSS is essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable
operation.
20150518
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