hip6018cb Intersil Corporation, hip6018cb Datasheet - Page 12

• Manufacturer Part Number: hip6018cb
• Description: Advanced Pwm And Dual Linear Power Control
• Manufacturer: Intersil Corporation

microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective
series inductance) parameters rather than actual capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor’s impedance with
frequency to select suitable components. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor. For a given transient
load magnitude, the output voltage transient response due to
the output capacitor characteristics can be approximated by
the following equation:
Linear Output Capacitors
The output capacitors for the linear regulator and the linear
controller provide dynamic load current. The linear controller
uses dominant pole compensation integrated in the error
amplifier and is insensitive to output capacitor selection.
Capacitor, C
regulation.
The output capacitor for the linear regulator provides loop
stability. The linear regulator (OUT2) requires an output
capacitor characteristic shown in Figure 13. The upper line
plots the 45 phase margin with 150mA load and the lower
line is the 45 phase margin limit with a 10mA load. Select a
C
Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
V
OUT2
TRAN
capacitor with characteristic between the two limits.
=
ESL
OUT3
×
dI
-------------------- -
TRAN
should be selected for transient load
dt
+
ESR
235
×
I
TR AN
HIP6018
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6018 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitors. Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: I
response time to the application of load, and t
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load, and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
ESR (Ω)
∆I
t
RISE
=
V
------------------------------- -
=
IN
F
0.7
0.6
0.5
0.4
0.3
0.2
0.1
TRAN
S
------------------------------- -
V
L
–
O
10
IN
FIGURE 13. C
×
V
L
×
OUT
–
O
I
V
is the transient load current step, t
TRAN
OUT
×
V
--------------- -
V
OU T
IN
OUT2
CAPACITANCE (µF)
t
FALL
OUTPUT CAPACITOR
∆V
100
=
OUT
L
------------------------------ -
O
V
=
×
OUT
I
∆I
TRAN
×
ESR
FALL
RISE
is the
is the
1000