hip6020 Intersil Corporation, hip6020 Datasheet - Page 8

• Manufacturer Part Number: hip6020
• Description: Advanced Dual Pwm And Dual Linear Power Controller
• Manufacturer: Intersil Corporation

Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC1 and OC2), linear
under-voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C
fully charged to 4.5V (UP signal). An under-voltage on either
linear output (VSEN3 and VSEN4) is ignored until after the
soft-start interval (T4 in Figure 6). This allows V
V
input voltage (+12V
counter and the fault latch.
Over-Voltage Protection
During operation, a short across the synchronous PWM
upper MOSFET (Q1) causes V
output exceeds the over-voltage threshold of 115% of
DACOUT, the over-voltage comparator trips to set the fault
latch and turns the lower MOSFET (Q2) on. This blows the
input fuse and reduces V
FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 8 illustrates the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the inductor (L
the OVER-CURRENT2 comparator trips when the voltage
across Q3 (i
R
capacitor (C
counter. C
with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4.5V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4.5V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.
The PWM1 controller operates in the same way as PWM2 to
over-current faults. Additionally, the two linear controllers
monitor the VSEN pins for an under-voltage. Should
OUT4
OCSET
to increase without fault at start-up. Cycling the bias
. This inhibits all outputs, discharges the soft-start
SS
D
SS
DS(ON)
recharges at T2 and initiates a soft-start cycle
•
) with a 28 A current sink, and increments the
r
DS(ON)
IN
to monitor the current for protection
on the VCC pin off then on) resets the
) exceeds the level programmed by
OUT1
2-288
. The fault latch raises the
OUT1
to increase. When the
OUT2
). At time T1,
OUT3
and
SS
is
HIP6020
excessive currents cause VSEN3 or VSEN4 to fall below the
linear under-voltage threshold, the LUV signal sets the over-
current latch, providing C
signal during the C
outputs to build above the under-voltage threshold during
normal operation. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistors (R
trip levels for each PWM converter. As shown in Figure 9, the
internal 200 A current sink (I
R
enables the over-current comparator (OVER-CURRENT1 or
OVER-CURRENT2). When the voltage across the upper
MOSFET (V
comparator trips to set the over-current latch. Both V
V
R
DS
OCSET
OCSET
i
OC
D
CURRENT
10V
are referenced to V
OVER-
0A
OVER-CURRENT TRIP:
0V
4V
2V
0V
PWM
r
DS ON
(V
helps V
V DS
FIGURE 5. OVER-CURRENT OPERATION
FIGURE 6. OVER-CURRENT DETECTION
SET
+
-
T0
OCSET1
DS(ON)
COUNT
= 1
>
OVERLOAD
>
) that is referenced to V
T1
APPLIED
OCSET
V SET
CONTROL
I OCSET
SS
GATE
) exceeds V
and R
charge interval allows the linear
I
OCSET
DRIVE
IN
200 A
track the variations of V
OCSET
T2
SS
R OCSET
and a small capacitor across
OCSET2
OCSET
is fully charged. Blanking the LUV
COUNT
SET
TIME
= 2
REPORTED
VCC
FAULT
) program the over-current
, the over-current
) develops a voltage across
UGATE
PHASE
R
V PHASE
IN
V OCSET
V
OCSET
. The DRIVE signal
SET
T3
+
=
IN
=
COUNT
V
V IN V DS
IN
V IN V SET
= 3
i
due to
D
V
T4
+
= +5V
SET
DS
–
–
and