hip6500b Intersil Corporation, hip6500b Datasheet
hip6500b
Related parts for hip6500b
hip6500b Summary of contents
Page 1
... TM Data Sheet Multiple Linear Power Controller with ACPI Control Interface The HIP6500B complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates two linear controllers and two regulators, switching, monitoring and control functions into a 20-pin SOIC package. One linear controller generates the 3.3V voltage plane from the ATX supply’ ...
Page 2
Block Diagram 12V 12V MONITOR 10.8V/9.8V TO 5VSB EA3 + - TO UV 3V3SB DETECTOR FAULT/MSEL UV DETECTOR TO 5VSB COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5VSB EA4 - + 3V3 ...
Page 3
... OUT3 3.3V DUAL C OUT3 FAULT SLP_S3 SLP_S5 EN5VDL EN3VDL SHUTDOWN 3 HIP6500B SB LINEAR REGULATOR 3.3V LINEAR CONTROLLER HIP6500B FIGURE 2. 12V 3V3 3V3SB 5V 3V3DLSB 3V3DL FAULT/MSEL HIP6500B R SEL S3 S5 EN5VDL EN3VDL GND FIGURE 3. Q1 LINEAR V MEM CONTROLLER 2.5V/3.3V V LINEAR CLK REGULATOR 2.5V CONTROL LOGIC 5VSB Q1 DRV2 ...
Page 4
... Regulation (Note 2) VSEN2 Nominal Voltage Level VSEN2 Nominal Voltage Level VSEN2 Undervoltage Rising Threshold VSEN2 Undervoltage Hysteresis (Note 3) VSEN2 Output Current 4 HIP6500B Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package +0.3V 12V Maximum Junction Temperature (Plastic Package .150 Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s) ...
Page 5
... FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 6) Shutdown-Level Threshold (Note 6) NOTES: 2. Sleep state only f9or 3.3V setting 3. Valid for 3.3V setting only ambient temperatures less than 50 5. Guaranteed by correlation. 6. Guaranteed by design. 5 HIP6500B SYMBOL TEST CONDITIONS I 5VSB = 5V DRV2 SEL R = 10k SEL ...
Page 6
... ATX outputs case of an overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB. 6 HIP6500B SS (Pin 16) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1 F recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages ...
Page 7
... This pin is the output of the internal 3. This internal regulator operates continuously for as OUT1 long as the 5VSB bias voltage is applied to the HIP6500B. This pin is monitored for under-voltage events. VCLK (Pin 6) This pin is the output of the internal 2.5V clock chip regulator (V ). This internal regulator operates only in active ...
Page 8
... TIMING DIAGRAM FOR DUAL DUAL EN3VDL = 1, EN5VDL = 0 8 HIP6500B Not shown in these diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise filter (typically s). This feature is useful in noisy computer environments if the control signals have to travel over signifi ...
Page 9
... TIME FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL OUTPUTS ENABLED) 9 HIP6500B Figure 9 shows the soft-start sequence for the typical application start-up in sleep state with all output voltages enabled. At time T0 5VSB (bias) is applied to the circuit. At time T1 the 5VSB surpasses POR level. An internal fast ...
Page 10
... IN IN temperature cycling occurs until the fault-causing condition output capacitors is removed. In HIP6500B applications, loss of any one active ATX output (3.3V IN monitors) during active state operation causes the chip to switch to S5 sleep state, in addition to reporting the input UV condition on the FAULT/MSEL pin. Exiting from this forced- ...
Page 11
... The built-in soft-start circuitry allows tight control of the slew- up speed of the output voltages controlled by the HIP6500B, thus enabling power-ups free of supply drop-off events. Since the outputs are ramped linear fashion, the ...
Page 12
... If the ATX supply does not meet the specifications, certain imbalances between the ATX’s outputs and the HIP6500B’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to the supplied outputs. At the transition between active and sleep states, this phenomena could result in the 5VSB voltage dropping below the POR level (typically 4 ...
Page 13
... Transistor Selection/Considerations The HIP6500B usually requires one P-Channel (or bipolar PNP), two N-Channel MOSFETs and two bipolar NPN transistors. One important criteria for selection of transistors for all the linear regulators/switching elements is package selection for efficient removal of heat. The power dissipated in a linear ...
Page 14
... 12V 3V3 5VSB 3V3SB 5V 3V3DLSB 3V3DL C10 U1 220 F HIP6500B FAULT/MSEL R1 1K EN5VDL EN3VDL C13 GND 0.1 F FIGURE 14. TYPICAL HIP6500B APPLICATION DIAGRAM + C2 220 DRV2 Q1 2SD1802 VSEN2 + C6,7 C8 2X150 VCLK C11 + C12 150 5VDLSB FDV304P DLA Q5 ...
Page 15
... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 15 HIP6500B M20.3-P 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL ...