lm96511ccsm National Semiconductor Corporation, lm96511ccsm Datasheet - Page 7

• Manufacturer Part Number: lm96511ccsm
• Description: Lm96511 Ultrasound Receive Analog Front End Afe
• Manufacturer: National Semiconductor Corporation

U10
V17
P17
N14
G14
F14
A17
B11
K14
L17
A6
B5
K15
K16
A1
A2
A3
B1
B22
A22
V31
U32
P32
L32
J32
G32
E32
C32
V32
T32
N32
K32
H32
F32
D32
B32
(Row_Column)
Ball Id.
ADC DOUT CH0+
ADC DOUT CH1+
ADC DOUT CH2+
ADC DOUT CH3+
ADC DOUT CH4+
ADC DOUT CH5+
ADC DOUT CH6+
ADC DOUT CH7+
ADC DOUT CH0-
ADC DOUT CH1-
ADC DOUT CH2-
ADC DOUT CH3-
ADC DOUT CH4-
ADC DOUT CH5-
ADC DOUT CH6-
ADC DOUT CH7-
DVGA INIT MSB
AMP CW/DVGA
DVGA INIT LSB
CW/DVGA RST
DVGA PA HI
DVGA CLK
CW Q CH0
CW Q CH1
CW Q CH2
CW Q CH3
CW Q CH4
CW Q CH5
CW Q CH6
CW Q CH7
ADC CLK+
ADC CLK-
Pin Name
DVGA UP
DVGA PD
AMP RST
LNA PD
Function
Output
Output
Input
Input
Amplifier Controls
ADC Signals
7
Description
CW DOPPLER Quadrature-Phase output current
DVGA GAIN Clock
1 = Increment DVGA gain
0 = Decrement DVGA gain
DVGA Initial Gain Control. Sets the initial DVGA gain. See
application section.
1 = CW DOPPLER Phase and DVGA Gain Reset
0 = B-mode
1 = CW DOPPLER mode
1 = LNA Power-down
1 = DVGA Power-down
1 = Reset all Amplifier SPI™ Registers
Post Amplifier Gain:
1= 38 dB
0= 31 dB
Differential Input Clock. The input clock must lie in the range of 40
MHz to 50 MHz. It is used by the PLL to generate the internal
sampling clocks .
Differential Serial Outputs for channels 0 to 7. Each pair of outputs
provides the serial output for the specific channel. The default
output is LVDS format, but programming the appropriate control
registers, the output format can be changed to SLVS .
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100Ω resistors.
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