lm9617 National Semiconductor Corporation, lm9617 Datasheet
lm9617
Related parts for lm9617
lm9617 Summary of contents
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... LM9617 CMOS Image Sensor VGA 30 FPS Monochrome General Description The LM9617 is a high performance, low power, third inch VGA CMOS Active Pixel Sensor capable of capturing grey-scale digi- tal still or motion images and converting them to a digital data stream. In addition to the active pixel array, an on-chip 12 bit A/D conver- tor, fixed pattern noise elimination circuits and a video gain is provided ...
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... Clock Gen (sequencer) mclk extsync Connection Diagram sclk snapshot resetb pdwn vss_dig vdd_dig hsync vsync pclk mclk d0 NC Ordering Information LM9617 CCEA Confidential AMP 12 Bit A/D Horizontal Gain Timing Control Register Bank Power Master Timer Control irq snapshot pdwn Figure 1. Chip Block Diagram 6 5 ...
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... Scan Read Out Direction (0,0) lens Figure 3. Scan directions and position of origin in imaging system Confidential Camera Control Serial Control Bus LM9617 Digital Video Bus Figure 2. Typical Application Diagram pin 1 digital out (0,0) horizontal scan CMOS Image Sensor ...
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Pin Descriptions Pin Name I/O Typ 1 vsrvdd vrl vdd_pix irq sadr sda sclk snapshot resetb ...
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Pin Descriptions (Continued) Pin Name I/O Typ d10 d11 vdd_od2 vss_od2 vdd_ana2 ...
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Absolute Maximum Ratings Any Positive Supply Voltage Voltage On Any Input or Output Pin Input Current at any pin (Note 3) ESD Susceptibility (Note 5) Human Body Model Machine Model Package Input Current (Note 3) Package Power Dissipation @ T ...
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Video Amplifier Specifications The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for Symbol Parameter Video Amplifier Nominal Gain AC Electrical Characteristics The following specifications apply for All VDD pins = +3.3V. Boldface limits ...
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CMOS Active Pixel Array Specifications Parameter Number of pixels (column, row) Total Active Array size (x,y Dimensions) Total Active Pixel Pitch Fill Factor (without micro-lens) Image Sensor Specifications The following specifications apply for All VDD pins = +3.3V, T 700nm, ...
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Sensor Response Curves 1.20E+03 1.00E+03 8.00E+02 6.00E+02 4.00E+02 2.00E+02 0.00E+00 370 420 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 0.05 Confidential 470 520 570 620 670 wavelength [nm] Figure 5. Spectral Response Curve 0.1 0.15 Exposure ...
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... Functional Description 1.0 OVERVIEW 1.1 Light Capture and Conversion The LM9617 contains a CMOS active pixel array consisting of 648 rows by 488 columns. This active region is surrounded by 8 columns and 8 rows of optically shielded (black) pixels as shown in Figure. 648 columns, 488 rows mono-chrome active pixels 8 columns, 8 rows ...
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Functional Description (continued) 2.0 WINDOWING The integrated timing and control circuit allows any size window in any position within the active region of the array to be read out with a 1x1 pixel resolution. The window read out is called ...
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Functional Description (continued) 4.0 SUBSAMPLING MODES 4.1 2:1 Sub-Sampling The timing and control circuit can be programmed to sub-sam- ple pixels in the display window vertically, horizontally or both, with an aspect ratio of 2:1 as illustrated in Figure16 Column/Horizontal ...
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... Functional Description (continued) 5.0 SNAPSHOT MODE The LM9617 is capable of capturing a single frame of an image under hardware or software control, with or without the aid of an external shutter. Two registers, SNAPSHOTMODE0 SNAPSHOTMODE1, are provided to program, monitor and con- trol all snapshot sequences. 5.1 Software Controlled Snapshots ...
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Functional Description (continued) snapshot SnapShotPol SnapEnable FTriggerNow Figure 19. Snapshot Trigger Generation Logic VIDEO c:TRIGGER==1 SNAP PREVIEW Figure 20. Auto Snapshot Mode State Diagram 5.4 CPU Snapshot Mode In CPU snapshot mode, the FTriggerEN is not set automatically and an ...
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... Functional Description (continued) 6.0 CLOCK GENERATION MODULE The LM9617 contains a clock generation module that will create two clocks as follows: Hclk, the horizontal clock. This is an internal system clock and can be programmed to be the input clock (mclk) or mclk divided by any number between 1 and 255. ...
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Functional Description (continued) Frame Row n Row 0 Row 1 Delay Programmable Row Delay Programmable Row Delay 7.3 Frame Rate Programming Guide The table bellow can be used as a guide for programming the sensor. Note that it is assumed ...
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... This block can be switched off by the user. 8.2 Black Level Compensation In addition to the programmable gain the LM9617 has a built in black level compensation block as illustrated in Figure 25. This block can be switched off. only enabled for black pixels input signal ...
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Functional Description (continued) 11.0 OFFSET ADJUSTMENT For maximum image quality over a wide range of light conditions it is necessary to set an appropriate offset voltage before using the sensor to capture images. This offset voltage must be applied to ...
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... The value for sadr is set at power up. 13.3 Acknowledgment The LM9617 will hold the value of the sda pin to a logic 0 during the logic 1 state of the Acknowledge clock pulse on sclk as shown in Figure 28. sda MSB ...
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... LM9617 LM9617 Connected bit Digital Image Processors Figure 34. Example of connection to 10/8 bit systems Synchronisation Signals in Master Mode default the sensor’s digital video port’s synchronisation sig- nals are configured to operate in master mode. In master mode ...
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Functional Description (continued) , pclk d[11:0] a) pclk active edge negative pclk d[11:0] b) pclk active edge positive invalid pixel data Figure 36. pclk in Data Ready Mode By default the pixel clock is a free running active low (pixel ...
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Functional Description (continued) pclk vsync hsync d[11: row1 frame 1 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay ...
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... Only two synchronization signals are used in slave mode as fol- lows: hsync is the row trigger input signal. vsync is the frame trigger input signal. Figure 46 shows the LM9617’s digital video port in slave mode connected to a digital video processor master DVP. d[11:0] din[11:0] hsync RowTrig ...
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MEMORY MAP ADDR Register 00h 01h REV 02h MCFG0 03h MCFG1 04h PCR 05h VCLKGEN 06h VMODE0 07h VMODE1 08h VMODE2 09h SNAPMODE0 0Ah SNAPMODE1 0Bh SROWS 0Ch SROWE 0Dh 0Eh DROWS 0Fh DROWE 10h DCOLS 11h DCOLE 12h DWLSB ...
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... Register Set The following section describes all available registers in the LM9617 register bank and their function. Register Name Device Rev Register Mnemonic REV Address 01 Hex Type Read Only. Bit Bit Symbol Description 7:0 SiRev The silicon revision register. Register Name Main Configuration 0 ...
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Register Set (continued) Register Name Hclk Generator Register Address 05 Hex Mnemonic VCLKGEN Type Read/Write Reset Value 04 Hex. Bit Bit Symbol Description 7:0 HclkGen Use to divide the frequency of the sensors master clock input, mclk to generate the ...
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Register Set (continued) Register Name Snapshot Mode Configuration Register 0 Address 09 Hex Mnemonic SNAPMODE0 Type Read/Write Reset Value 00 Hex Bit Bit Symbol Description 7.6 SsFrames Program to set the number of frames required before readout during a snapshot ...
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Register Set (continued) Register Name Scan Window Row Start Register Address 0B Hex Mnemonic SROWS Type Read/Write Reset Value 00 Hex Bit Bit Symbol Description 7:0 SwStartRow Use to program the scan window’s start row address MSBs. If bit 6 ...
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Register Set (continued) Register Name Integration Time High Register Address 13 Hex Mnemonic ITIMEH Type Read/Write Reset Value 00 Hex. Bit Bit Symbol Description 7:4 Reserved 3:0 Itime[11:8] Program to set the integration time of the array. The value pro- ...
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Register Set (continued) Register Name Black Level Compensation Register Address 26 Hex Mnemonic BLCOEFF Type Read/Write Reset Value 00 Hex Bit Bit Symbol Description 7:0 Alpha[7:0] Exponential averaging coeffi- cient for black pixels Register Name Threshold 0 High Register Address ...
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Timing Information 1.0 DIGITAL VIDEO PORT MASTER MODE TIMING pclk hsync t1 d[11:0] pclk vsync t5 hsync pclk vsync hsync F n-1 F n-2 delay delay Inter Frame Delay Figure 51. Frame Delay Timing (With Inter Frame Delay). Label Descriptions ...
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Timing Information (continued) d[11:0] hsync vsync pclk Figure 52. d[11:0], hsync & vsync to Active High pclk Timing d[11:0] hsync vsync pclk Figure 53. d[11:0], hsync & vsync to Active Low pclk Timing The following specifications apply for all supply ...
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Timing Information (continued) 2.0 DIGITAL VIDEO PORT SLAVE MODE TIMING trigger row n hsync t2 d[11:0] P652 P653 P654 mclk Row n-1 Figure 54. Slave Mode Row Trigger and Readout Timing hsync trigger last row in frame n vsync mclk ...
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Timing Information (continued) 3.0 DIGITAL VIDEO PORT SINGLE FRAME CAPTURE (SNAPSHOT MODE) TIMING snapshot or FTriggerNow irq FTriggerEn extsync or FtSync FtBusy Figure 57. Snapshot Mode Timing With External Shutter snapshot or FTriggerNow irq FTriggerEn extsync or FtSync FtBusy Figure ...
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Timing Information (continued) 4.0 SERIAL BUS TIMING Sr t fDA SDA t t SU;STA HD;STA SCLK t rCL = Rp resistor pull-up = MCS current source pull-up (1) Rising edge of the first SCLK pulse after an acknowledge bit. The ...
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Array Mechanical Information 43 .085 +/-.010 [2.16 +/- 0.25] 42 .020 +/-.003 [0.51 +/- 0.07] TYP 31 30 .040 +/-.007 TYP [1.02 +/- 0.17] Optical Center of Sensor Array .102 MAX [2.58] Notes: 1. Controlling dimensions are in inches, values ...
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... NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or ...