cat64lc40 Catalyst Semiconductor, cat64lc40 Datasheet - Page 7

• Manufacturer Part Number: cat64lc40
• Description: 4k-bit Spi Serial Eeprom
• Manufacturer: Catalyst Semiconductor

a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC40 requires an active LOW CS in order to
be selected. Each instruction must be preceded by a
HIGH-to-LOW transition of CS before the input of the 4-
bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Figure 4. Write Instruction Timing
Figure 5. Ready/BUSY
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
RDY/BUSY
RDY/BUSY
RESET
RESET
DO
SK
CS
* Please check instruction set table for address
DO
DI
CS
SK
DI
WRITE INSTRUCTION
BUSY
BUSY
BUSY
BUSY Status Instruction Timing
1
0
HIGH
LOW
1
0
0
1
0
0
ADDRESS*
7
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
D15
NEXT INSTRUCTION
D0
CAT64LC40
Doc. No. 1021, Rev. A
PD
after