W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 119

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

port,
CRF1 (Default 0x00)
and
power
transmitting a
ERR# pins.
transmitting a
Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume
Bit 6: Device's trap status.
Bit 6: URCTRAPSTS. UART C trap status.
Bit 5 - 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
Bit 3: PRTTRAPSTS. Printer port trap status.
Bit 2: FDCTRAPSTS. FDC trap status.
Bit 1: URATRAPSTS. UART A trap status.
event occurs. Upon setting this bit, the sleeping/working state machine will transition the
system to the working state. This bit is only set by hardware and is cleared by writing a 1 to
this bit position or by the sleeping/working state machine automatically when the global
standby timer expires.
= 0
= 1
IRQ, and external input to the device. The device's idle timer reloads the preset expiry
depending on which device wakes up. These 5 bits are controlled by the UART C, printer
FDC, UART A and UART B power down machines respectively . Writing a 1 clears this bit
writing a 0 has no effect. Note that: the user is not supposed to change the status while
management function is enabled.
These bits of trap status indicate that the individual device Wakes-Up due to any I/O access,
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
the chip is in the sleeping state.
the chip is in the working state.
UART C is now in the sleeping state.
UART C is now in the working state due to any UART C access, any IRQ, the
the printer port is now in the sleeping state.
the printer port is now in the workinging state due to any printer port access, any IRQ,
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
UART A is now in the sleeping state.
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
any DMA acknowledge, and any transition on BUSY, ACK#, PE, SLCT, and
acknowledge, and any enabling of the motor enable bits in the DOR register.
receiver begins receiving a start bit, the transmitter shift register begins
start bit, and any transition on MODEM control input lines.
start bit, and any transition on MODEM control input lines.
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Publication Release Date: April 2003
W83977EF
Revision 1.1