bd95710muv-e2 ROHM Co. Ltd., bd95710muv-e2 Datasheet - Page 5

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bd95710muv-e2

Manufacturer Part Number
bd95710muv-e2
Description
2phase Switching Regulator Controllers Graphic Card
Manufacturer
ROHM Co. Ltd.
Datasheet
●Pin Descriptions
© 2009 ROHM Co., Ltd. All rights reserved.
BD95710MUV
www.rohm.com
・UGATE1 (Pin 1), UGATE2 (Pin 18)
・BOOT1 (Pin 2), BOOT2 (Pin 17)
・5VCC (Pin 3)
・AGND (Pin 4 , Pin12)
・BUSEN (Pin 5)
・CsN1 (Pin 6), CsP2 (Pin 9), CsN1 (Pin 7), CsN2 (Pin 8)
・IMAX / IOUT (Pin 10)
・RT (Pin 11)
・FB (Pin 13)
・PGND (Pin 14)
・REFIN/EN/EN (Pin 15)
・IREFOUT/POK (Pin 16)
・PHASE1 (Pin 24), PHASE2 (Pin 19)
・LGATE1 (Pin 23), LGATE2 (Pin 20)
・VCCDRV (Pin 21)
・VCC (Pin 22)
These are the voltage supply pins to drive the Gate of the high side FET. This voltage PHASEings between BOOT1/2 and
PHASE1/2. High-speed Gate driving for the high side FET is achieved due to the low on-resistance (3 ohm when UG is high,
2 ohm when UG is low) of the driver.
These are the voltage supply pins to drive the high side FET. The maximum absolute ratings are 35V (from GND) and 15V
(from PHASE1/2). BOOT1/2 voltages swing between VIN+VCC and VCC during active operation.
This is the internal 5V regulator output pin. The minimum output current capability is 20mA.
This is the ground pin for IC internal circuits. It is equivalent to FIN voltage.
This pin monitors the supply input VIN through resistance divider. The POR rising threshold level is set to 0.8V.
These pins are connected to both sides of the current sense resistance or Inductance (DCR sensing) to detect output
current.
This pin has multiple functions such as the output current indication, OCP (Over Current Protection) limit setting, and the
output voltage load line adjustment pin. BD95710MUV detects the voltage between Cs+ pin and Cs- pin and limits the
output current (OCP) using resistance connected between IMAX/IOUT/Droop and GND. A very low current sense resistor or
inductor DCR can also be used for this platform.
This is the pin to adjust the switching frequency based on the resistance value. The frequency range is f=50KHz - 1000KHz.
This is the output voltage feedback pin. It is possible to adjust the output voltage using external resistor divider based on the
equation, REFIN/EN≒FB. However, FB becomes 0.6V when REFIN/EN=5VCC.
This is the power ground pin connected to the source of the low side FET.
This is an internal or external reference voltage selectable pin. If REFIN/EN is pulled up to 5VCC, internal reference voltage
(0.6V) is used. If REFIN/EN is driven by an external voltage ranged 0.4V to 3.3V, external voltage of REFIN/EN voltage is
used. It is very convenient for synchronizing external voltage supply. The IC controls the output voltage (REFIN/EN≒FB).
And also this pin is used for enable function. If REFIN/EN is less than 0.3V, the whole circuit is shut down.
This pin is internal reference voltage output and power good output. During start up, this pin voltage is low. This pin
becomes high impedance when FB pin voltage goes beyond 75% of specified FB voltage after soft start ends.
These are the source pins for the high side FET. The maximum absolute ratings are 15V (from GND). PHASE1/2 voltage
swings between VIN and GND.
This is the voltage supply to drive the Gate of the low side FET. This voltage swings between VCC and PGND. High-speed
Gate driving for the low side FET is achieved due to the low on-resistance (2 ohm when LGATE1/2 is high, 0.5 ohm when
LGATE1/2 is low) of the driver.
This is the supply voltage pin to drive an external NPN/N_MOSFET for 8V linear regulator. The maximum absolute rating is
15V.
This is the power supply pin for IC internal circuit and driver circuit. The maximum circuit current is 10mA. There are 3
usages depending on a supply voltage for driver (5V, 8V, and 12V). It is recommended that a 0.1uF bypass capacitor be put
in this pin to avoid voltage fluctuation when the VCC is supplied from 5V or 12V rail directly from the actual platforms. If 8V
is used for the supply voltage, this pin is connected to the LDO output. In this case, it is recommended that at least 10uF
ceramic capacitor be input to avoid oscillation.
5/20
Technical Note
2009.04 - Rev.B

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