zl2103 Intersil Corporation, zl2103 Datasheet - Page 13

• Manufacturer Part Number: zl2103
• Description: 3a Digital-dc Synchronous Step-down Dc/dc Converter
• Manufacturer: Intersil Corporation

Power Conversion Functional
Description
Internal Bias Regulators and Input Supply
Connections
The ZL2103 employs three internal low dropout (LDO) regulators
to supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
• VR: The VR LDO provides a regulated 7V bias supply for the
• VRA: The VRA LDO provides a regulated 5V bias supply for the
• V2P5:The V2P5 LDO provides a regulated 2.5V bias supply for
When the input supply (VDDS) is higher than 7.5V, the VR and
VRA pins should not be connected to any other pins. These pins
should only have a filter capacitor attached. Due to the dropout
voltage associated with the VR and VRA bias regulators, the
VDDS pin must be connected to these pins for designs operating
from a supply below 7.5V. Figure 13 illustrates the required
connections for all cases.
high-side MOSFET driver circuit. It is powered from the VDDS
pin and supplies bias current internally. A 4.7µF filter capacitor
is required at the VR pin. The VDDS pin directly supplies the
low-side MOSFET driver circuit.
current sense circuit and other analog circuitry. It is powered
from the VDDS pin and supplies bias current internally. A
4.7µF filter capacitor is required at the VRA pin.
the main controller circuitry. It is powered from the VRA LDO
and supplies bias current internally. A 10µF filter capacitor is
required at the V2P5 pin.
STEP #
1
2
3
4
5
4.5V ≤ V
VDDS
VRA
VR
FIGURE 13. INPUT SUPPLY CONNECTIONS
IN
Internal Memory Check
Multi-mode Pin Check
≤ 5.5V
V
IN
Pre-ramp Delay
Power Applied
Device Ready
STEP NAME
5.5V < V
VDDS
VRA
VR
13
IN
≤ 7.5V
V
IN
Input voltage is applied to the ZL2103’s VDD pins (VDDP and VDDS).
The device is ready to accept an enable signal.
The device will check for values stored in its internal memory. This step
is also performed after a Restore command.
The device loads values configured by the multi-mode pins.
The device requires approximately 2ms following an enable signal and
prior to ramping its output. Additional pre-ramp delay may be
configured using the SS pin.
7.5V < V
VDDS
VRA
VR
TABLE 3. ZL2103 START-UP SEQUENCE
IN
≤ 14V
V
IN
ZL2103
DESCRIPTION
Note: The internal bias regulators, VR and VRA, are not designed
to be outputs for powering other circuitry. Do not attach external
loads to any of these pins. Only the multi-mode pins may be
connected to the V2P5 pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, C
When the lower MOSFET (QL) is turned on, the SW node is pulled
to ground and the capacitor is charged from the internal VR bias
regulator through diode D
MOSFET (QH) turns on, the SW node is pulled up to VDDP and the
voltage on the bootstrap capacitor is boosted approximately 6.5V
above VDDP to provide the necessary voltage to power the high-
side driver. An internal Schottky diode is used with C
maximize the high-side drive supply voltage.
Output Voltage Selection
The output voltage may be set to any voltage between 0.6V and
5.0V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification. Using the
pin-strap method, V
voltages as shown in Table 2.
TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS
OPEN
VSET
HIGH
LOW
OUT
can be set to one of three standard
B
. When QL turns off and the upper
ignore an enable signal or PMBus
Approx 5ms to 10ms (device will
Depends on input supply ramp
traffic during this period)
Approximately 2ms
TIME DURATION
B
time
(see Figure 9).
-
V
1.2V
1.5V
3.3V
OUT
B
to help
May 3, 2011
FN6966.5