hcs165ms Intersil Corporation, hcs165ms Datasheet

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hcs165ms

Manufacturer Part Number
hcs165ms
Description
Radiation Hardened Inverting 8-bit Parallel-input/serial Output Shift Register
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS165MS is a Radiation Hardened 8-Bit Paral-
lel-In/Serial-Out Shift Register with complementary serial
outputs and an asynchronous parallel load input.
The HCS165MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS165MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS165DMSR
HCS165KMSR
HCS165D/Sample
HCS165K/Sample
HCS165HMSR
Bit-Day (Typ)
- Standard Outputs - 10 LSTTL Loads
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
8-Bit Parallel-Input/Serial Output Shift Register
C
2
/mg
-9
o
o
C
C
Errors/
240
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
GND
SCREENING LEVEL
CP
Q7
PL
D4
D5
D6
D7
HCS165MS
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
Radiation Hardened Inverting
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
CP
Q7
PL
D4
D5
D6
D7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
Spec Number
9
File Number
PACKAGE
VCC
CE
D3
D2
D1
D0
DS
Q7
VCC
CE
D3
D2
D1
D0
DS
Q7
518757
2481.2

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hcs165ms Summary of contents

Page 1

... The HCS165MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS165MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... L = LOW voltage level l = LOW voltage level one setup time prior to the LOW-to-High clock transition Qn = Lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition Don’t Care = LOW-to-HIGH clock transition. HCS165MS ...

Page 3

... Functional Test VIH = 0.70(VCC), VIL = 0.30(VCC) (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCS165MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS165MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH Specifications HCS165MS (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0 ...

Page 6

... Each pin except VCC and GND will have a resistor of 1k OPEN 7, 9 NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS165MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCS165MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS165MS AC Load Circuit TPHL ...

Page 9

... CP (2) D4 (3) D5 (4) D6 (5) (6) D7 NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCS165 is TA14385A. HCS165MS HCS165MS CE PL VCC (1) (16) (15) (7) (8) (9) GND ...

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