hcs195ms Intersil Corporation, hcs195ms Datasheet
hcs195ms
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hcs195ms Summary of contents
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... The HCS195MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS195MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...
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... INPUTS referenced input (or output) one set-up time prior to clock level one set-up time prior to clock = positive clock HCS195MS TRUTH TABLE ...
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... VIL = 0.30(VCC), (Note 3) NOTES: 1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCS195MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . ...
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... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS195MS GROUP (NOTES 1, 2) ...
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... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH Specifications HCS195MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP ...
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... Each pin except VCC and GND will have a resistor of 1k OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS195MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS195MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...
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... INPUT VIH VIL TSU CP INPUT VIH VS VIL TH = Hold Time TSU = Setup Time TW = Pulse Width AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 HCS195MS AC Load Circuit TPHL TTHL 80% 20% UNITS Load Circuit TH TW UNITS 287 DUT TEST POINT ...
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... J (2) K (3) D0 (4) D1 (5) (6) D2 NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCS195 is TA14387A. HCS195MS HCS195MS Q0 MR VCC (1) (16) (15) (7) (8) (9) GND ...