attiny11 ATMEL Corporation, attiny11 Datasheet
attiny11
Available stocks
Related parts for attiny11
attiny11 Summary of contents
Page 1
... Packages – 8-pin PDIP and SOIC • Operating Voltages – 1.8 - 5.5V for ATtiny12V-1 – 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4 – 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8 • Speed Grades – 1.2 MHz (ATtiny12V-1) – MHz (ATtiny11L-2) – MHz (ATtiny12L-4) – MHz (ATtiny11-6) – ...
Page 2
... Device Flash EEPROM ATtiny11L 1K - ATtiny11 1K - ATtiny12V ATtiny12L ATtiny12 The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Register Voltage Range Frequency 32 2.7 - 5.5V 0-2 MHz 32 4.0 - 5.5V 0-6 MHz 32 1.8 - 5.5V 0-1.2 MHz 32 2.7 - 5.5V 0-4 MHz 32 4 ...
Page 3
... The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. ...
Page 4
... ATtiny12 Block Diagram ATtiny11/12 4 Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM six general-purpose I/O lines, 32 general-purpose working regis- ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con- tinue functioning ...
Page 5
... Ground pin. Port 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below ...
Page 6
... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single-register operations are also executed in the ALU. Figure 2 shows the ATtiny11/12 AVR RISC microcontroller architecture. The AVR uses a Har- vard architecture concept with separate memories and buses for program and data memories ...
Page 7
... Some microcontrollers in the AVR prod- uct family feature a hardware multiplier in the arithmetic part of the ALU. The ATtiny11/12 uses a 3-level-deep hardware stack for subroutines and interrupts. The hardware stack is 9 bits wide and stores the program counter (PC) return address while subroutines and interrupts are executed ...
Page 8
... General-purpose Register File ATtiny11/12 8 Figure 4 shows the structure of the 32 general-purpose registers in the CPU. Figure 4. AVR CPU General-purpose Working Registers 7 General- purpose Working Registers R30 (Z-register low byte) R31 (Z-register high byte) All the register operating instructions in the instruction set have direct- and single-cycle access to all registers ...
Page 9
... The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc- tion Set description for detailed information. Note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. ATtiny11/ ...
Page 10
... Table 8 on page 23 and Table 10 on page 25. The internal RC oscillator option is an on-chip oscillator running at a fixed frequency of 1 MHz in ATtiny11 and 1.2 MHz in ATtiny12. If selected, the device can operate with no external components. The device is shipped with this option selected. On ATtiny11, the Watchdog Oscillator is used as a clock, while ATtiny12 uses a separate calibrated oscillator ...
Page 11
... For details on how to choose R and C, see Table 29 on page 61. The external RC oscillator is sensitive to noise from neighboring pins, and to avoid problems, PB5 (RESET) should be used as an output or reset pin, and PB4 should be used as an out- put pin. Figure 7. External RC Configuration ATtiny11/12 PB4 (XTAL2) XTAL1 GND PB4 (XTAL2) XTAL1 GND 11 ...
Page 12
... Register Description Oscillator Calibration Register – OSCCAL ATtiny11/12 12 Bit $31 CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove pro- cess variations from the oscillator frequency. When OSCCAL is zero, the lowest available frequency is chosen ...
Page 13
... Note: Reserved and unused locations are not shown in the table. All the different ATtiny11/12 I/O and peripherals are placed in the I/O space. The differ- ent I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
Page 14
... Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr ATtiny11/12 14 Figure 8. Direct Single-register Addressing The operand is contained in register d (Rd). Figure 9. Indirect Register Addressing The register accessed is the one pointed to by the Z-register (R31, R30). Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd) ...
Page 15
... Program execution continues at address The relative address k is -2048 to 2047. Figure 13. Code Memory Constant Addressing 15 Z-REGISTER Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). ATtiny11/12 PROGRAM MEMORY 1 0 $000 $1FF 15 ...
Page 16
... Memory Access and Instruction Execution Timing ATtiny11/12 16 This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. ...
Page 17
... Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/erase cycles. The ATtiny11/12 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory. See “Memory Programming” on page 48 for a detailed description on Flash memory programming ...
Page 18
... Register Description EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR ATtiny11/12 18 Bit $ EEAR5 Read/Write R R R/W Initial Value The EEPROM Address Register – EEAR specifies the EEPROM address in the 64-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. ...
Page 19
... The calibrated oscillator is used to time EEPROM. In Table 6 the typical programming time is listed for EEPROM access from the CPU. Table 6. Typical EEPROM Programming Times Number of Calibrated Parameter RC Oscillator Cycles EEPROM write (from CPU) 4096 ATtiny11/12 Min Programming Max Programming Time Time 3 ...
Page 20
... Sleep Modes for the ATtiny12 Idle Mode Power-down Mode ATtiny11/ enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction enabled interrupt occurs while the MCU sleep mode, the MCU awakes, executes the interrupt rou- tine, and resumes execution from the instruction following SLEEP ...
Page 21
... The period of the watchdog oscillator is 2.7 µs (nominal) at 3.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 62. When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective ...
Page 22
... The circuit diagram in Figure 15 shows the reset logic for the ATtiny11. Figure 16 shows the reset logic for the ATtiny12. Table 7 defines the electrical parameters of the reset circuitry for ATtiny11. Table 9 shows the parameters of the reset circuitry for ATtiny12. ...
Page 23
... The Watchdog Oscillator is used for timing the start-up time, and this oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 62. Table 8. Start-up Times for the ATtiny11 (V ...
Page 24
... ATtiny11/12 24 Figure 16. Reset Logic for the ATtiny12 Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL On-chip RC Oscillator Table 9. Reset Characteristics for the ATtiny12 Symbol Parameter Power-on Reset Threshold Voltage (rising) (1) V POT Power-on Reset Threshold Voltage (falling) RESET Pin Threshold V RST ...
Page 25
... Programmed 67 ms (at V The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 62. Note that the BODLEVEL fuse can be used to select start-up times even if the Brown- out Detection is disabled (by leaving the BODEN fuse unprogrammed). The device is shipped with CKSEL3..0 = 0010. ...
Page 26
... Power-on Reset for the ATtiny12 ATtiny11/ Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec- tion level is nominally 1.4V. The POR is activated whenever V level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail- ure in supply voltage. ...
Page 27
... Figure 20. Brown-out Reset during Operation (ATtiny12 BOT- RESET TIME-OUT INTERNAL RESET Note: The hysteresis BOT BOT + ATtiny11/12 t TOUT decreases below the trigger CC increases above the trig the voltage stays below the trigger level CC V BOT+ t TOUT = mV ...
Page 28
... Bit 7..2 - Res: Reserved Bits These bits are reserved bits in the ATtiny11 and always read as zero. • Bit 1 - EXTRF: EXTernal Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. ...
Page 29
... To use the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. ATtiny11/12 Reset Source Watchdog Reset ...
Page 30
... Reset and Interrupt ATtiny11/12 30 The ATtiny11 provides four different interrupt sources and the ATtiny12 provides five. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt ...
Page 31
... The ATtiny11/12 has two 8-bit Interrupt Mask control registers; GIMSK – General Inter- rupt Mask register and TIMSK – Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. ...
Page 32
... This bit is a reserved bit in the ATtiny11/12 and always reads as zero. • Bit 6 - Res: Reserved Bit in ATtiny11 This bit is a reserved bit in the ATtiny11 and always reads as zero. • Bit 6 - PUD: Pull-up Disable in ATtiny12 Setting this bit, disables all pull-ups on port B. If this bit is cleared, the pull-ups can be individually enabled as described in section “ ...
Page 33
... Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero. • Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin ...
Page 34
... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero ...
Page 35
... TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 - Res: Reserved bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero. ATtiny11/ ...
Page 36
... When PB5..3 are used for alternate functions, the values in the corresponding DDRB and PORTB bits are ignored the internal pull-ups are IL Device ATtiny11/12 ATtiny12 ATtiny11/12 ATtiny11/12 ATtiny12 ATtiny11/12 ATtiny12 ATtiny11/12 ATtiny11/12 ATtiny11/12 1006F–AVR–06/07 ...
Page 37
... Output No n: 4,3…0, pin number. Note that in ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. Because this pin is used for 12V programming, there is no ESD protection diode limiting the voltage on the pin 0.5V. Thus, special care should be taken to ensure that ...
Page 38
... Alternate Functions of Port B ATtiny11/12 38 All port B pins are connected to a pin change detector that can trigger the pin change interrupt. See “Pin Change Interrupt” on page 32 for details. In addition, Port B has the following alternate functions: • RESET - Port B, Bit 5 When the RSTDISBL fuse is unprogrammed, this pin serves as external reset. When the RSTDISBL fuse is programmed, this pin is a general input pin ...
Page 39
... Timer/Counter0 Timer/Counter Prescaler 1006F–AVR–06/07 The ATtiny11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase counter with an external pin connection that triggers the counting. ...
Page 40
... ATtiny11/12 40 Figure 23. Timer/Counter0 Block Diagram T0 1006F–AVR–06/07 ...
Page 41
... Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and always read as zero. • Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0 The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0. Table 18. Clock 0 Prescale Select CS02 ...
Page 42
... TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 - Res: Reserved bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero ...
Page 43
... Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and will always read as zero. • Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. • ...
Page 44
... Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 62. The WDR – Watchdog Reset – instruction should always be executed before the Watch- dog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings ...
Page 45
... When this bit is cleared, the normal input pin PB0 is applied to the positive input of the comparator. • Bit 6- Res: Reserved Bit in ATtiny11 This bit is a reserved bit in the ATtiny11 and will always read as zero. • Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output. ...
Page 46
... Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and will always read as zero. • Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator Inter- rupt ...
Page 47
... Thus, when BOD is not enabled, after setting the AINBG bit, the user must always allow the reference to start up before the output from the Analog Comparator is used. The bandgap reference uses approximately 10 µA, and to reduce power consumption in Power-down mode, the user can turn off the reference when entering this mode. ATtiny11/12 47 ...
Page 48
... Note the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny11 is in Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0. The ATtiny12 has eight fuse bits, BODLEVEL, BODEN, SPIEN, RSTDISBL and CKSEL3 ...
Page 49
... Flash location and write the value to the OSCCAL register. Atmel’s ATtiny11 offers 1K bytes of Flash Program memory. The ATtiny11 is shipped with the on-chip Flash Program memory array in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a High-voltage (12V) Serial programming mode. Only minor cur- rents (< ...
Page 50
... Not applicable ATtiny12V 2.2 - 5.5V ATtiny12L 2.7 - 5.5V ATtiny12 4.0 - 5.5V This section describes how to program and verify Flash Program memory, EEPROM Data memory (ATtiny12), lock bits and fuse bits in the ATtiny11/12. Figure 26. High-voltage Serial Programming 11.5 - 12.5V PB5 (RESET) PB3 (XTAL1) SERIAL CLOCK INPUT GND High-voltage Serial Programming 4 ...
Page 51
... Power-off sequence:Set PB3 to “0”. Set PB5 to “1”. Turn V power off. CC When writing or reading serial data to the ATtiny11/12, data is clocked on the rising edge of the serial clock, see Figure 27, Figure 28 and Table 24 for details. ATtiny11/12 and GND. Set PB5 and PB0 CC ...
Page 52
... Figure 27. High-voltage Serial Programming Waveforms SERIAL DATA INPUT PB0 SERIAL INSTR. INPUT PB1 SERIAL DATA OUTPUT MSB PB2 SERIAL CLOCK INPUT 0 XTAL1/PB3 Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 Instruction Instr.1 PB0 0_1000_0000_00 Chip Erase PB1 0_0100_1100_00 PB2 x_xxxx_xxxx_xx PB0 ...
Page 53
... Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 (Continued) Instruction Instr.1 PB0 0_0000_0000_00 Read EEPROM PB1 0_0110_1000_00 byte (ATtiny12) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny11) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny12) PB2 x_xxxx_xxxx_xx ...
Page 54
... High-voltage Serial Programming Characteristics Low-voltage Serial Downloading (ATtiny12 only) ATtiny11/12 54 Figure 28. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SCI (PB3) SDO (PB2) Table 24. High-voltage Serial Programming Characteristics T 5.0V ± 10% (Unless otherwise noted) Symbol Parameter t SCI (PB3) Pulse Width High SHSL t SCI (PB3) Pulse Width Low ...
Page 55
... Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be writ- ten. If polling is not used, wait t ATtiny11/12 value. WD_ERASE or t before transmitting the ...
Page 56
... Data Polling ATtiny11/12 56 next instruction. See Table 28 on page 58 for t an erased device, no $FFs in the data file(s) needs to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at the serial output MISO (PB1) pin. ...
Page 57
... A987 6543 xxxx xxxx xxxx xxxx A987 6543 ATtiny11/12 Operation Enable serial programming while RESET is low. Chip erase Flash and EEPROM memory arrays. Read H (high or low) data o from program memory at word address a:b. ...
Page 58
... Low-voltage Serial Programming Characteristics ATtiny11/12 58 Figure 31. Low-voltage Serial Programming Timing MOSI t OVSH SCK MISO Table 26. Low-voltage Serial Programming Characteristics 2.2 - 5.5V (Unless otherwise noted) CC Symbol Parameter 1/t Oscillator Frequency (V CLCL CC t Oscillator Period (V = 2.2 - 2.7V) CLCL CC 1/t Oscillator Frequency (V CLCL CC t Oscillator Period (V = 2.7 - 4.0V) CLCL CC 1/t Oscillator Frequency (V ...
Page 59
... Ground ................................-1. Voltage on RESET with respect to Ground......-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40 Current and GND Pins................................ 100 Characteristics – Preliminary Data T = -40°C to 85° 2.7V to 5.5V for ATtiny11 Symbol Parameter V Input Low Voltage IL V Input Low Voltage IL1 ...
Page 60
... DC Characteristics – Preliminary Data (Continued -40°C to 85° 2.7V to 5.5V for ATtiny11 Symbol Parameter I Power Supply Current CC Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input Leakage Current Analog Comparator T ACPD Propagation Delay Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. ...
Page 61
... External Clock Drive Waveforms 1006F–AVR–06/07 Figure 32. External Clock VIH1 VIL1 External Clock Drive ATtiny11 Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL External Clock Drive ATtiny12 V CC ...
Page 62
... ATtiny11 Typical Characteristics ATtiny11/12 62 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source. ...
Page 63
... Figure 35. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 2.5 3 3.5 ATtiny11/ FREQUENCY = 4 MHz ˚ 3 Device Clocked by Internal Oscillator ˚ ...
Page 64
... ATtiny11/12 64 Figure 36. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 Figure 37. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 5 4.5 4 3.5 3 2.5 2 1 Device Clocked by External 32kHz Crystal CC cc ...
Page 65
... Figure 38. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 39. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2.5 3 3.5 ATtiny11/ FREQUENCY = 4 MHz 3 Device Clocked by Internal Oscillator ˚ 4.5 5 5.5 ...
Page 66
... ATtiny11/12 66 Figure 40. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 2.5 3 3.5 Figure 41. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 1 Device Clocked by External 32kHz Crystal CC cc ...
Page 67
... Figure 42. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 2 2.5 3 Figure 43. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 ATtiny11/ ˚ 3.5 4 4.5 5 5 ˚ 3.5 4 4.5 5 5 ˚ ...
Page 68
... ATtiny11/12 68 Analog comparator offset voltage is measured as absolute offset. Figure 44. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 1.5 Common Mode Voltage (V) Figure 45. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. ...
Page 69
... ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 47. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 1.5 2 2.5 3 ATtiny11/ ˚ 3.5 4 4.5 5 5.5 6 6 ˚ 3.5 4 4.5 5 5.5 ...
Page 70
... ATtiny11/12 70 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 48. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 ˚ 0.5 1 1.5 Figure 49. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...
Page 71
... ˚ 0.5 1 Figure 51. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 0.5 1 1.5 ATtiny11/ 1.5 2 2 ˚ ˚ 2.5 3 3.5 4 4 ...
Page 72
... ATtiny11/12 72 Figure 52. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 53. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 0 2. ˚ C ˚ 1 1 2.7V CC ...
Page 73
... Figure 54. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 55. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATtiny11/ ˚ ˚ 5.0 5.0 73 ...
Page 74
... ATtiny12 Typical Characteristics ATtiny11/12 74 The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins config- ured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. ...
Page 75
... Figure 58. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 ATtiny11/12 , Device Clocked by External 32kHz Crystal ˚ ˚ A 3.5 4 4.5 5 5 Device Clocked by Internal Oscillator 3 ...
Page 76
... ATtiny11/12 76 Figure 59. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL ˚ 1.5 2 2.5 3 Analog Comparator offset voltage is measured as absolute offset. Figure 60. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. ...
Page 77
... ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 62. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 ATtiny11/ 2. ˚ 1 ˚ 3.5 4 4 (V) ...
Page 78
... ATtiny11/12 78 Figure 63. Calibrated RC Oscillator Frequency vs. V CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.22 1.2 1.18 1.16 1.14 1.12 1.1 1.08 1.06 2 2.5 3 3.5 Figure 64. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 1 ˚ ˚ 4.5 5 5 ˚ ...
Page 79
... Figure 65. Pull-up Resistor Current vs. Input Voltage (V 120 ˚ A 100 ˚ 0.5 1 1.5 Figure 66. Pull-up Resistor Current vs. Input Voltage ( ˚ ˚ 0.5 1 ATtiny11/ 2.5 3 3.5 4 4 2.7V) CC 1.5 2 2 ...
Page 80
... ATtiny11/12 80 Figure 67. I/O Pin Sink Current vs. Output Voltage ( 0.5 1 Figure 68. I/O Pin Source Current vs. Output Voltage ( ˚ ˚ 0.5 1 1 ˚ ˚ A 1.5 2 2 ...
Page 81
... Figure 69. I/O Pin Sink Current vs. Output Voltage ( 0.5 Figure 70. I/O Pin Source Current vs. Output Voltage ( ˚ ˚ 0.5 1 ATtiny11/12 = 2.7V ˚ ˚ 1 2.7V) CC 1.5 2 2 ...
Page 82
... ATtiny11/12 82 Figure 71. I/O Pin Input Threshold Voltage vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 72. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0. 25° 4.0 5 25° 4.0 5 1006F–AVR–06/07 ...
Page 83
... Register Summary ATtiny11 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 - $32 TCNT0 Timer/Counter0 (8 Bit) $31 Reserved $30 Reserved ... Reserved $22 Reserved $21 WDTCR - $20 Reserved $1F Reserved $1E Reserved $1D Reserved $1C Reserved $1B Reserved $1A Reserved $19 Reserved $18 PORTB - $17 DDRB - $16 PINB - $15 Reserved ...
Page 84
... Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. ATtiny11/12 84 Bit 6 ...
Page 85
... PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATtiny11/12 Flags #Clocks Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H ...
Page 86
... CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watch Dog Reset ATtiny11/12 86 Operation Rd ← (Z) (Z) ← ← ← ← ← ← (Z) I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← ...
Page 87
... Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 1006F–AVR–06/07 Ordering Code ATtiny11L-2PC ATtiny11L-2SC 2 ATtiny11L-2PI ATtiny11L-2SI (2) ATtiny11L-2SU ATtiny11-6PC ATtiny11-6SC ATtiny11-6PI 6 (2) ATtiny11-6PU ATtiny11-6SI (2) ATtiny11-6SU Package Type ATtiny11/12 Package Operation Range 8P3 Commercial (0°C to 70°C) 8S2 8P3 Industrial 8S2 (-40° ...
Page 88
... Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive). Also Halide free and fully Green. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) ATtiny11/12 88 Ordering Code Package ATtiny12V-1PC 8P3 ...
Page 89
... Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R 1006F–AVR–06/ TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) ATtiny11/ End View COMMON DIMENSIONS (Unit of Measure = inches) MIN MAX SYMBOL NOM A 0.210 A2 0.115 0.130 ...
Page 90
... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny11/ TOP VIEW ...
Page 91
... The revision numbers are referring to the document revision. 1. “Not recommended for new design”. 1. Updated chapter layout. 2. Updated Power-down in “Sleep Modes for the ATtiny11” on page 20. 3. Updated Power-down in “Sleep Modes for the ATtiny12” on page 20. 4. Updated Table 16 on page 36. ...
Page 92
... EEPROM Data Memory...................................................................................... 13 Memory Access and Instruction Execution Timing ............................................. 13 I/O Memory ......................................................................................................... 14 Reset and Interrupt Handling.............................................................................. 15 ATtiny12 Internal Voltage Reference.................................................................. 24 Interrupt Handling ............................................................................................... 25 Sleep Modes for the ATtiny11 ............................................................................ 31 Sleep Modes for the ATtiny12 ............................................................................ 31 ATtiny12 Calibrated Internal RC Oscillator ......................................................... 32 Timer/Counter0 ................................................................................... 33 Timer/Counter Prescaler..................................................................................... 33 Watchdog Timer.................................................................................. 36 ATtiny12 EEPROM Read/Write Access............................................. 38 Prevent EEPROM Corruption ...
Page 93
... Low-voltage Serial Downloading (ATtiny12 only) ............................................... 52 Low-voltage Serial Programming Characteristics............................................... 56 Electrical Characteristics................................................................... 57 Absolute Maximum Ratings ................................................................................ 57 DC Characteristics – Preliminary Data ............................................................... 57 External Clock Drive Waveforms ........................................................................ 59 External Clock Drive ATtiny11 ............................................................................ 59 External Clock Drive ATtiny12 ............................................................................ 59 ATtiny11 Typical Characteristics ........................................................................ 60 ATtiny12 Typical Characteristics ........................................................................ 72 Register Summary ATtiny11.............................................................. 81 Register Summary ATtiny12.............................................................. 82 Instruction Set Summary ...
Page 94
... Product Contact Web Site Technical Support www.atmel.com Enter Product Line E-mail Literature Requests www.atmel.com/literature ® , logo and combinations thereof, are the registered trademarks of Atmel Corporation or Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Sales Contact www.atmel.com/contacts 1006F– ...