attiny11 ATMEL Corporation, attiny11 Datasheet - Page 42
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attiny11
Manufacturer Part Number
attiny11
Description
8-bit Microcontroller With 1k Byte Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY11.pdf
(94 pages)
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Timer/Counter Interrupt Mask
Register – TIMSK
Timer/Counter Interrupt Flag
Register – TIFR
42
ATtiny11/12
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag
(Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
• Bits 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
Bit
$39
Read/Write
Initial Value
Bit
$38
Read/Write
Initial Value
R
R
7
0
7
0
-
-
R
R
6
0
6
0
-
-
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R
3
0
-
R
3
0
-
R
2
0
R
-
2
0
-
TOIE0
TOV0
R/W
R/W
1
0
1
0
1006F–AVR–06/07
R
0
0
R
-
0
0
-
TIMSK
TIFR