atmega603 ATMEL Corporation, atmega603 Datasheet - Page 3

• Manufacturer Part Number: atmega603
• Description: 8-bit Microcontroller With 64k/128k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power Save mode, the timer
oscillator continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density
non-volatile memory technology. The on-chip ISP Flash
allows the program memory to be reprogrammed in-system
through a serial interface or by a conventional nonvolatile
memory programmer. By combining an 8-bit RISC CPU
with a large array of ISP Flash on a monolithic chip, the
Atmel ATmega603/103 is a powerful microcontroller that
provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega603/103 AVR is supported with a full suite of
program and system development tools including: C com-
pilers, macro assemblers, program debugger/simulators,
in-circuit emulators, and evaluation kits.
Comparison Between ATmega 603 and
ATmega 103
The ATmega603 has 64K bytes of In-System Programma-
ble Flash, 2K bytes of EEPROM, and 4K bytes of internal
SRAM. The ATmega603 does not have the ELPM instruc-
tion.
The ATmega103 has 128K bytes of In-System Program-
mable Flash, 4K bytes of EEPROM, and 4K bytes of inter-
nal SRAM. The ATmega103 has the ELPM instruction,
necessary to reach the upper half of the Flash memory for
constant table lookup.
Table 1 summarizes the different memory sizes for the two
devices.
Table 1. Memory Size Summary
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can pro-
vide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20 mA and can drive LED
displays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Part
ATmega603
ATmega103
64K bytes
128K bytes
Flash
EEPROM
2K bytes
4K bytes
4K bytes
SRAM
4K bytes
Port A serves as Multiplexed Address/Data bus when using
external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low, will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port C (PC7..PC0)
Port C is an 8-bit Output port. The Port C output buffers can
sink 20 mA.
Port C also serves as Address output when using external
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up
resistors. The Port E output buffers can sink 20 mA. As
inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port E also serves the functions of various special features.
Port F (PF7..PF0)
Port F is an 8-bit Input port. Port F also serves as the ana-
log inputs for the ADC.
RESET
input. A low on this pin for two machine cycles while the
oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
TOSC1
Input to the inverting Timer/Counter oscillator amplifier
TOSC2
Output from the inverting Timer/Counter oscillator amplifier
WR
External SRAM Write Strobe.
RD
External SRAM Read Strobe.
ALE
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
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