dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 208

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dspic33fj128mc706at-i-pt

Manufacturer Part Number
dspic33fj128mc706at-i-pt
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 19-2:
DS70594A-page 206
bit 4
bit 3
bit 2
bit 1
bit 0
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I
RBF: Receive Buffer Full Status bit
1 = Receive complete; I2CxRCV is full
0 = Receive not complete; I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
Preliminary
2
C device address byte.
2
C slave)
© 2009 Microchip Technology Inc.

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