dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 335

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

PORTD
PORTE
PORTF
PORTG
Power-Saving Features .................................................... 153
Program Address Space ..................................................... 35
Program Memory
Q
Quadrature Encoder Interface (QEI) ................................. 191
Quadrature Encoder Interface (QEI) Module
R
Reader Response ............................................................. 336
Registers
© 2009 Microchip Technology Inc.
Register Map............................................................... 61
Register Map............................................................... 61
Register Map............................................................... 61
Register Map............................................................... 62
Clock Frequency and Switching................................ 153
Construction................................................................ 68
Data Access from Program Memory
Data Access from Program Memory Using
Data Access from, Address Generation...................... 69
Memory Map ............................................................... 35
Table Read High Instructions
Table Read Low Instructions
Visibility Operation ...................................................... 71
Interrupt Vector ........................................................... 36
Organization................................................................ 36
Reset Vector ............................................................... 36
Register Map............................................................... 50
ADxCHS0 (ADCx Input Channel 0 Select) ............... 250
ADxCHS123 (ADCx Input
ADxCON1 (ADCx Control 1)..................................... 244
ADxCON2 (ADCx Control 2)..................................... 246
ADxCON3 (ADCx Control 3)..................................... 247
ADxCON4 (ADCx Control 4)..................................... 248
ADxCSSH (ADCx Input Scan Select High)............... 251
ADxCSSL (ADCx Input Scan Select Low) ................ 251
ADxPCFGH (ADCx Port Configuration High) ........... 252
ADxPCFGL (ADCx Port Configuration Low)............. 252
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 228
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 229
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 229
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 230
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 226
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 227
CiCTRL1 (ECAN Control 1) ...................................... 218
CiCTRL2 (ECAN Control 2) ...................................... 219
CiEC (ECAN Transmit/Receive Error Count)............ 225
CiFCTRL (ECAN FIFO Control)................................ 221
CiFEN1 (ECAN Acceptance Filter Enable) ............... 228
CiFIFO (ECAN FIFO Status)..................................... 222
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)...... 232
CiFMSKSEL2 (ECAN Filter
CiINTE (ECAN Interrupt Enable) .............................. 224
CiINTF (ECAN Interrupt Flag)................................... 223
CiRXFnEID (ECAN Acceptance Filter n
Using Program Space Visibility........................... 71
Table Instructions ............................................... 70
TBLRDH ............................................................. 70
TBLRDL .............................................................. 70
Channel 1, 2, 3 Select) ..................................... 249
15-8 Mask Selection) ........................................ 233
Extended Identifier)........................................... 231
dsPIC33FJXXXMCX06A/X08A/X10A
Preliminary
CiRXFnSID (ECAN Acceptance Filter n
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 235
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 235
CiRXMnEID (ECAN Acceptance Filter
CiRXMnSID (ECAN Acceptance Filter
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 236
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 236
CiTRBnDLC (ECAN Buffer n
CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 239
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 238
CiTRBnSID (ECAN Buffer n Standard Identifier)...... 238
CiTRBnSTAT (ECAN Receive Buffer n Status)........ 240
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 237
CiVEC (ECAN Interrupt Code) ................................. 220
CLKDIV (Clock Divisor) ............................................ 148
CORCON (Core Control) ...................................... 28, 90
DFLTxCON (Digital Filter x Control) ......................... 194
DMACS0 (DMA Controller Status 0) ........................ 139
DMACS1 (DMA Controller Status 1) ........................ 141
DMAxCNT (DMA Channel x Transfer Count) ........... 138
DMAxCON (DMA Channel x Control)....................... 135
DMAxPAD (DMA Channel x
DMAxREQ (DMA Channel x IRQ Select) ................. 136
DMAxSTA (DMA Channel x RAM Start
DMAxSTB (DMA Channel x RAM Start
DSADR (Most Recent DMA RAM Address) ............. 142
I2CxCON (I2Cx Control)........................................... 203
I2CxMSK (I2Cx Slave Mode Address Mask)............ 207
I2CxSTAT (I2Cx Status) ........................................... 205
ICxCON (Input Capture x Control)............................ 172
IEC0 (Interrupt Enable Control 0) ............................. 103
IEC1 (Interrupt Enable Control 1) ............................. 105
IEC2 (Interrupt Enable Control 2) ............................. 107
IEC3 (Interrupt Enable Control 3) ............................. 109
IEC4 (Interrupt Enable Control 4) ............................. 111
IFS0 (Interrupt Flag Status 0) ..................................... 94
IFS1 (Interrupt Flag Status 1) ..................................... 96
IFS2 (Interrupt Flag Status 2) ..................................... 98
IFS3 (Interrupt Flag Status 3) ................................... 100
IFS4 (Interrupt Flag Status 4) ................................... 102
INTCON1 (Interrupt Control 1) ................................... 91
INTCON2 (Interrupt Control 2) ................................... 93
INTTREG (Interrupt Control and Status) .................. 130
IPC0 (Interrupt Priority Control 0) ............................. 112
IPC1 (Interrupt Priority Control 1) ............................. 113
IPC10 (Interrupt Priority Control 10) ......................... 122
IPC11 (Interrupt Priority Control 11) ......................... 123
IPC12 (Interrupt Priority Control 12) ......................... 124
IPC13 (Interrupt Priority Control 13) ......................... 125
IPC14 (Interrupt Priority Control 14) ......................... 126
IPC15 (Interrupt Priority Control 15) ......................... 127
IPC16 (Interrupt Priority Control 16) ......................... 128
IPC17 (Interrupt Priority Control 17) ......................... 129
IPC2 (Interrupt Priority Control 2) ............................. 114
IPC3 (Interrupt Priority Control 3) ............................. 115
IPC4 (Interrupt Priority Control 4) ............................. 116
IPC5 (Interrupt Priority Control 5) ............................. 117
IPC6 (Interrupt Priority Control 6) ............................. 118
Standard Identifier) ........................................... 231
Mask n Extended Identifier).............................. 234
Mask n Standard Identifier) .............................. 234
Data Length Control) ........................................ 239
Peripheral Address).......................................... 138
Address Offset A) ............................................. 137
Address Offset B) ............................................. 137
DS70594A-page 333