dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 151

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

10.0
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04 and dsPIC33FJ128GPX02/X04 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed
dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/
X04 devices can manage power consumption in four
ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
10.1
dsPIC33FJ32GP302/304,
and dsPIC33FJ128GPX02/X04 devices allow a wide
range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
EXAMPLE 10-1:
© 2009 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note:
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
This data sheet summarizes the features
of
dsPIC33FJ64GPX02/X04
dsPIC33FJ128GPX02/X04
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”,
“Section
Power-Saving
which is available from the Microchip web-
site (www.microchip.com).
power.
the
PWRSAV INSTRUCTION SYNTAX
9.
Watchdog
dsPIC33FJ32GP302/304,
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04
; Put the device into SLEEP mode
; Put the device into IDLE mode
Modes”
Timer
families
(DS70196),
and
and
Preliminary
of
10.2
dsPIC33FJ32GP302/304,
and dsPIC33FJ128GPX02/X04 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake up.
10.2.1
The following occur in Sleep mode:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate,
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals can continue
• Any peripheral that requires the system clock
The device wakes up from Sleep mode on any of these
events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
since the system clock source is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
source for its operation is disabled.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
dsPIC33FJ64GPX02/X04
DS70292C-page 149