dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 381

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

MPLAB Integrated Development Environment Software .. 313
MPLAB PM3 Device Programmer .................................... 315
MPLAB REAL ICE In-Circuit Emulator System................. 315
MPLINK Object Linker/MPLIB Object Librarian ................ 314
N
NVM Module
O
Open-Drain Configuration ................................................. 156
Output Compare ............................................................... 193
P
Packaging ......................................................................... 363
Peripheral Module Disable (PMD) .................................... 150
PICSTART Plus Development Programmer ..................... 316
Pinout I/O Descriptions (table) ............................................ 15
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 80
Power-Saving Features .................................................... 149
Program Address Space ..................................................... 35
Program Memory
R
Reader Response ............................................................. 382
Register Map
Registers
© 2009 Microchip Technology Inc.
ulator ......................................................................... 315
Register Map............................................................... 59
Details ....................................................................... 364
Marking ..................................................................... 363
Register Map............................................................... 59
Register Map......................................................... 57, 58
Register Map............................................................... 58
Clock Frequency and Switching................................ 149
Construction................................................................ 65
Data Access from Program Memory Using Program
Data Access from Program Memory Using Table Instruc-
Data Access from, Address Generation...................... 66
Memory Map ............................................................... 35
Table Read Instructions
Visibility Operation ...................................................... 68
Interrupt Vector ........................................................... 36
Organization................................................................ 36
Reset Vector ............................................................... 36
CRC ............................................................................ 57
Dual Comparator......................................................... 57
Parallel Master/Slave Port .......................................... 56
Real-Time Clock and Calendar................................... 57
AD1CHS0 (ADC1 Input Channel 0 Select ................ 259
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 258
AD1CON1 (ADC1 Control 1) .................................... 253
AD1CON2 (ADC1 Control 2) .................................... 255
AD1CON3 (ADC1 Control 3) .................................... 256
AD1CON4 (ADC1 Control 4) .................................... 257
AD1CSSL (ADC1 Input Scan Select Low)................ 260
AD1PCFGL (ADC1 Port Configuration Low) ............ 260
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 229
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 230
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 230
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 231
Space Visibility.................................................... 68
tions .................................................................... 67
TBLRDH ............................................................. 67
TBLRDL .............................................................. 67
Preliminary
CiCFG1 (ECAN Baud Rate Configuration 1)............ 227
CiCFG2 (ECAN Baud Rate Configuration 2)............ 228
CiCTRL1 (ECAN Control 1)...................................... 220
CiCTRL2 (ECAN Control 2)...................................... 221
CiEC (ECAN Transmit/Receive Error Count) ........... 227
CiFCTRL (ECAN FIFO Control) ............................... 223
CiFEN1 (ECAN Acceptance Filter Enable)............... 229
CiFIFO (ECAN FIFO Status) .................................... 224
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 233,
CiINTE (ECAN Interrupt Enable) .............................. 226
CiINTF (ECAN Interrupt Flag) .................................. 225
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 236
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 236
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 237
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 237
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 239,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 238
CiVEC (ECAN Interrupt Code) ................................. 222
CLKDIV (Clock Divisor) ............................................ 143
CORCON (Core Control)...................................... 28, 89
DCICON1 (DCI Control 1) ........................................ 244
DCICON2 (DCI Control 2) ........................................ 245
DCICON3 (DCI Control 3) ........................................ 246
DCISTAT (DCI Status) ............................................. 247
DMACS0 (DMA Controller Status 0) ........................ 132
DMACS1 (DMA Controller Status 1) ........................ 134
DMAxCNT (DMA Channel x Transfer Count)........... 131
DMAxCON (DMA Channel x Control)....................... 128
DMAxPAD (DMA Channel x Peripheral Address) .... 131
DMAxREQ (DMA Channel x IRQ Select) ................. 129
DMAxSTA (DMA Channel x RAM Start Address A) . 130
DMAxSTB (DMA Channel x RAM Start Address B) . 130
DSADR (Most Recent DMA RAM Address) ............. 135
I2CxCON (I2Cx Control)........................................... 205
I2CxMSK (I2Cx Slave Mode Address Mask)............ 209
I2CxSTAT (I2Cx Status) ........................................... 207
IFS0 (Interrupt Flag Status 0) ............................. 93, 100
IFS1 (Interrupt Flag Status 1) ............................. 95, 102
IFS2 (Interrupt Flag Status 2) ............................. 97, 104
IFS3 (Interrupt Flag Status 3) ............................. 98, 105
IFS4 (Interrupt Flag Status 4) ............................. 99, 106
INTCON1 (Interrupt Control 1) ................................... 90
INTCON2 (Interrupt Control 2) ................................... 92
INTTREG Interrupt Control and Status Register ...... 123
IPC0 (Interrupt Priority Control 0) ............................. 107
IPC1 (Interrupt Priority Control 1) ............................. 108
IPC11 (Interrupt Priority Control 11) ......................... 117
IPC14 (Interrupt Priority Control 14) ......................... 118
IPC15 (Interrupt Priority Control 15) ......................... 119
IPC16 (Interrupt Priority Control 16) ......................... 120
IPC17 (Interrupt Priority Control 17) ......................... 121
IPC18 (Interrupt Priority Control 18) ......................... 122
IPC2 (Interrupt Priority Control 2) ............................. 109
IPC3 (Interrupt Priority Control 3) ............................. 110
IPC4 (Interrupt Priority Control 4) ............................. 111
IPC5 (Interrupt Priority Control 5) ............................. 112
IPC6 (Interrupt Priority Control 6) ............................. 113
234
fier) ................................................................... 233
fier) ................................................................... 232
Identifier) .......................................................... 235
Identifier) .......................................................... 235
240, 242
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