dspic33fj16gs404t-i-pt Microchip Technology Inc., dspic33fj16gs404t-i-pt Datasheet - Page 223

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dspic33fj16gs404t-i-pt

Manufacturer Part Number
dspic33fj16gs404t-i-pt
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
REGISTER 16-3:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application
SPIFSD
R/W-0
U-0
SPIxCON2: SPIx CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
FRMPOL
R/W-0
U-0
U-0
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
U-0
U-0
x = Bit is unknown
FRMDLY
R/W-0
U-0
DS70318D-page 221
U-0
U-0
bit 8
bit 0

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