atxmega128a4-mu ATMEL Corporation, atxmega128a4-mu Datasheet
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atxmega128a4-mu
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atxmega128a4-mu Summary of contents
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... Building control Motor control • • Board control Networking • • White Goods Optical • Hand-held battery applications • Power tools • HVAC • Metering • Medical Application 8/16-bit XMEGA Microcontroller ATxmega64A4 ATxmega32A4 ATxmega16A4 ATxmega128A4 Advance Information 8069A–AVR–02/08 ...
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Block Diagram/Pinout INDEX CORNER AC5/ADC5/PA5 AC6/ADC6/PA6 AC7/ADC7/PA7 AREF/ADC8/PB0 ADC9/PB1 DAC0/ADC10/PB2 DACB1/ADC11/PB3 GND VCC SDA/OC0A/_OC0A/PC0 SCL/XCK0/OC0B/OC0A/PC1 ATxmega Port R 2 DATA BU S OSC/CLK 3 Control BOD VREF POR ADC A 4 TEMP RTC OCD Power Control ...
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... Ordering Code Flash (B) ATxmega128A4-AU 128K + 4K ATxmega64A4-AU 64K + 4K ATxmega32A4-AU 32K + 4K ATxmega16A4-AU 16K + 4K ATxmega128A4-MU 128K + 4K ATxmega64A4-MU 64K + 4K ATxmega32A4-MU 32K + 4K ATxmega16A4-MU 16K + 4K Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green ...
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... AVR instructions in a single clock cycle, the XMEGA A4 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 5. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com. 5.1 Recommended reading • ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 139 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...
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Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Reprogrammable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Bootloader Section ...
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Figure 7-1. EFFF F000 FFFF 10000 10FFF The Application Table- and Boot sections can also be used for general application software. 7.4 SRAM Data Memory The XMEGA A4 has internal SRAM memory for data storage. The Memory Map for the ...
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I/O Memory All XMEGA A4 I/Os and peripherals are addressable through I/O memory locations in the data memory space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose registers ...
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DMA - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...
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Event System 9.1 Features • Inter peripheral communication and signalling • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be generated by ...
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Figure 9-1. The the event routing network can directly connect together ADCs, DACs, Analog Comparators (AC), I/O ports (PORT), the Real-time Counter (RTC), and Timer/Counters (T/C). Events can also be generated from software (CPU). ATxmega A4 12 Event System Block ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run time clock switching • 4 Internal Oscillators; 32 MHz, 2 MHz, 32 kHz, 32 kHz Ultra Low Power (ULP) • 0 MHz Crystal ...
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Figure 10-1. Clock system overview Run-time Calibrated Run-time Calibrated Each clock source is briefly described in the following sub-sections. ATxmega KHz ULP Internal Oscillator 32 KHz Calibrated Internal Oscillator 32 KHz Crystal Oscillator 0 MHz ...
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Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock source based on internal components only intended mainly for system ...
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Power Management and Sleep Modes 11.1 Features • 5 sleep modes – IDLE – Power-down – Power-save – Standby – Extended standby • Power Reduction register to disable clock to unused peripheral 11.2 Overview The XMEGA A4 provides various ...
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Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that the system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or ...
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System Control and Reset 12.1 Resetting the AVR During reset, all I/O Registers are set to their initial values. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should be a JMP - Absolute ...
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WDT - Watchdog Timer 12.3.1 Features • 11 selectable timeout period, from 8s. • Two operation modes – Standard mode – Window mode • Runs from 1 kHz Ultra Low Power clock reference • Configuration lock ...
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PMIC - Programmable Multi-level Interrupt Controller 13.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 13-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x044 IVEC_PORTB_INT_base 0x04E IVEC_ADCB_INT_base 0x056 IVEC_PORTE_INT_base 0x05A IVEC_TWIE_INT_base 0x05E IVEC_TIMERE0_INT_base 0x074 IVEC_USARTE0_INT_base 0x07A IVEC_USARTE1_INT_base 0x080 IVEC_PORTD_INT_base 0x084 IVEC_PORTA_INT_base 0x088 IVEC_ACA_INT_base 0x08E IVEC_ADCA_INT_base 0x096 IVEC_TWID_INT_base 0x09A IVEC_TIMERD0_INT_base 0x0A6 IVEC_TIMERD1_INT_base ...
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I/O Ports 14.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 14-1. I/O configuration - Totem-pole 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input) 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input) 14.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down Figure 14-6. I/O configuration - Wired-AND with optional pull-up ATxmega A4 24 DIRn OUTn INn OUTn INn INn OUTn Pn Pn ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level The basic input sensing may be synchronous or asynchronous and is built on the configuration shown in Figure 14-7. Input sensing ...
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T/C - 16-bits Timer/Counter with PWM 15.1 Features • 3 Timer/Counter 0 (Timer0) • 2 Timer/Counter 1 (Timer1) • True 16-bit Design • Double Buffered Timer Period Setting • Compare or Capture Channels are Double Buffered • 4 Combined ...
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AWEX - Advanced Waveform Extension 16.0.1 Features • 4-DTI Units (8-pin) • 8-bit Resolution • Separate High and Low Side Dead-Time Setting • Double Buffered Dead-Time • Fault Protection (Event Controlled) • Single Channel Multiple Output Operation (for BLDC ...
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RTC - Real-Time Counter 17.1 Features • 16-bit Timer • Flexible Tick resolution ranging from kHz • 1 Compare register • 1 Top Value register • Clear timer on Overflow or Compare Match • Overflow ...
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TWI - Two-Wire Interface 18.1 Features • 3 Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows ...
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SPI - Serial Peripheral Interface 19.1 Features • 2 Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 20.1 Features • 5 Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 21.1 Features • Pulse modulation/demodulation for infrared communication • IrDA 1.4 Compatible for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed pulse period, ...
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Crypto Engine 22.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and Decryption – DES and triple-DES supported – Single-cycle DES instruction – Encryption/Decryption in 16 clock ...
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ADC - 12-bit Analog to Digital Converter 23.1 Features • Two ADCs with 12-bit resolution • 2 Msps conversion rate for each ADC • Signed- and Unsigned conversions • 4 result registers with individual input channel control for each ...
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Figure 23-1. ADC overview Each ADC has 4 registers defining a MUX selection with a corresponding result register. This means that 4 channels may be sampled within 1.5 µs without any intervention by the application other than starting the conversion, ...
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DAC - 12-bit Digital to Analog Converter 24.1 Features • One DAC with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous time or 2 ...
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AC - Analog Comparator 25.1 Features • Two Analog Comparators • Selectable Power vs. Speed – 20 µA/500 ns active current consumption/propagation delay or – 130 µA/30 ns active current consumption/propagation delay • Selectable hysteresis – mV, ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 25-1 on page ...
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OCD - On-chip Debug 26.1 Features • Complete Program Flow Control – Symbolic Debugging Support in Hardware – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor • 1 dedicated program address breakpoint or symbolic breakpoint for AVR ...
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Program, Debug and Test Interfaces 27.1 Features • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) • Access to the OCD system • Programming of Flash, EEPROM, Fuses and Lock Bits 27.2 Overview The PDI is the ...
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Pinout The pinout of XMEGA A4 is shown in I/O functionality, each pin may have several function. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can ...
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Oscillators TOSCn XTALn 28.1.6 DEBUG/SYSTEM functions TEST PROG RESET PDI_CLK PDI_DATA 28.2 Alternate Pin Functions The tables below shows the main and alternate pin functions for all pins on each port. It also shows which peripheral which make use ...
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Table 28-3. Port C - Alternate functions PORT C PIN # INTERRUPT TCC0 GND 8 VCC 9 PC0 10 SYNC OC0A PC1 11 SYNC OC0B PC2 12 SYNC/ASYNC OC0C PC3 13 SYNC OC0D PC4 14 SYNC PC5 15 SYNC PC6 ...
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Electrical Characteristics - TBD 29.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0. Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ...
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ADC Characteristics – TBD Table 29-1. ADC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Conversion Time ADC Clock Frequency DC Supply Voltage Source Impedance Start-up time AVCC Analog Supply Current Table 29-2. ...
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DAC Characteristics – TBD Table 29-3. DAC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Calibrated Gain/Offset Error Output Range Output Settling Time Output Capacitance Output Resistance Reference Input Voltage Reference Input Capacitance ...
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Typical Characteristics - TBD 8069A–AVR–02/08 ATxmega A4 47 ...
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Peripheral Module Address Map The address maps shows the base address for each peripheral and module in XMEGA A4. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...
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Packaging information 32.1 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...
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D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. 2325 Orchard Parkway San Jose, CA 95131 R ATxmega Pin #1 ...
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Errata 33.1 All rev. No known errata. 8069A–AVR–02/08 ATxmega A4 51 ...
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Datasheet Revision History 34.1 8069A – 02/08 1. ATxmega A4 52 Initial revision. 8069A–AVR–02/08 ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Block Diagram/Pinout .............................................................................. 2 2 Ordering Information ............................................................................... 3 3 Disclaimer ................................................................................................. 4 4 Overview ................................................................................................... 4 5 Resources ................................................................................................. 4 5.1Recommended reading .............................................................................................4 6 AVR CPU ................................................................................................... 5 ...
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Power Management and Sleep Modes ................................................. 16 11.1Features ................................................................................................................16 11.2Overview ................................................................................................................16 11.3Sleep Modes ..........................................................................................................16 12 System Control and Reset .................................................................... 18 12.1Resetting the AVR .................................................................................................18 12.2Reset Sources .......................................................................................................18 12.3WDT - Watchdog Timer .........................................................................................19 13 PMIC - Programmable Multi-level Interrupt ...
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IRCOM - IR Communication Module ..................................................... 32 21.1Features ................................................................................................................32 21.2Overview ................................................................................................................32 22 Crypto Engine ......................................................................................... 33 22.1Features ................................................................................................................33 22.2Overview ................................................................................................................33 23 ADC - 12-bit Analog to Digital Converter ............................................. 34 23.1Features ................................................................................................................34 23.2Overview ................................................................................................................34 24 ...
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Characteristics – TBD ...................................................................................46 29.5Analog Comparator Characteristics – TBD ...........................................................46 30 Typical Characteristics - TBD ............................................................... 47 31 Peripheral Module Address Map .......................................................... 48 32 Packaging information .......................................................................... 49 32.144A ........................................................................................................................49 32.244M1 ......................................................................................................................50 33 Errata ....................................................................................................... 51 33.1All rev. ...
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ATxmega A4 v ...
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